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Anthropic is building a custom silicon team to support its world-class AI training and inference workloads. This role is for an experienced silicon engineer with deep expertise in one or more key domains: front-end design, pre-silicon verification, physical design, design for test, analog and mixed-signal, technology and foundry, CAD/design infrastructure, or packaging/signal/power integrity.
You will operate with significant autonomy on a small, high-impact team covering a large technical surface. Key responsibilities include: owning end-to-end program activities from strategy through execution; writing specifications and interface definitions that guide the broader design; making and owning consequential technical decisions (technology selection, build-vs-buy-vs-license, design authority allocation); contributing AI-assisted approaches to your domain and helping the team understand where Claude genuinely accelerates work; participating in architecture discussions from your specialty's perspective; partnering with inference, performance, kernels, and infrastructure teams on hardware-software co-design; and supporting first-silicon bring-up and debug.
Minimum qualifications include: deep, hands-on expertise in at least one silicon domain with direct personal contribution to taped-out and shipped silicon you can speak to in detail; working fluency in adjacent domains sufficient to reason about chip-level tradeoffs; experience working with external partners (ASIC houses, IP vendors, foundries, test partners) and holding technical bars; a track record of owning directional technical decisions and their consequences; practical experience using AI coding tools; and clear communication skills with ability to drive alignment across teams.
Preferred experience includes: machine learning accelerators or high-performance compute designs; founding or early-stage silicon teams; both partner-executed and in-house programs; chip-package-system interface familiarity; hardware-software co-design; building AI-assisted design/verification flows; and depth in memory subsystems, on-die interconnect, numerics, or low-power design.
This is a role for someone who has shipped silicon, maintains realistic relationships with schedules, and is comfortable making consequential calls with high autonomy and minimal organizational scaffolding.
