SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 240,000 - 333,000 / annual
Raxium, a Google-owned semiconductor company with revolutionary display technology, is seeking a Senior CMOS Test and Validation Lead to drive the bring-up, characterization, and high-volume manufacturing (HVM) release of next-generation Analog Mixed-Signal (AMS) ASICs. This is a critical technical leadership role bridging design, DFT, and product engineering teams.
You will lead and mentor a small team of test and validation engineers through the entire post-silicon lifecycle, from first-silicon bench bring-up to ATE production release. Key responsibilities include partnering with IC Design and DFT teams during pre-tapeout to define post-silicon test processes and design requirements, designing and debugging multi-site ATE test programs (Advantest V93000 or Teradyne UltraFLEX) for high-efficiency parallel testing of digital and AMS blocks, and driving exhaustive post-silicon validation across PVT corners.
You will ensure strict bench-to-ATE correlation for critical high-speed interfaces and analog blocks, oversee the architecture and schematic review of complex loadboards and probe cards to meet Signal Integrity and Power Integrity standards for high-frequency measurements, and automate data collection from wafer test. The role requires deep expertise in CMOS test engineering, post-silicon validation, and technical leadership with the ability to solve ambiguous problems and influence stakeholders.
Required qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; 10+ years in Test Engineering and Post-Silicon Validation with 5+ years in CMOS; 2+ years in technical leadership or lead architect role; experience with Analog Mixed-Signal Silicon; and programming skills for lab automation and data analysis. Preferred: Master's or PhD in EE/CS; experience with benchtop measurement equipment (oscilloscopes, spectrum analyzers, BERTs, VNAs); vendor management with OSATs and PCB houses; familiarity with high-speed serial protocols (MIPI); and proven track record developing C++/Python test code for automated test equipment.
