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PCB Layout Engineer, Robotics

OpenAI - San Francisco, CA, United States - Hybrid - posted 2026-09-01

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OpenAI's Robotics team is seeking an experienced PCB Layout Engineer to design high-density electronics for next-generation robotic systems. You will own the complete PCB layout lifecycle—from floor planning through fabrication release—working in close collaboration with electrical, signal/power integrity (SI/PI), mechanical, and manufacturing teams. Key responsibilities include: - Owning PCB layout, component placement, routing, and fabrication release for complex robotic systems - Collaborating with SI/PI engineers to refine layouts based on simulation results - Implementing high-speed routing, controlled impedance, power distribution, decoupling, grounding, EMI/EMC, thermal, and mechanical-integration requirements - Working directly with PCB fabricators and assembly partners to define stack-ups, establish design rules, and drive DFM/DFA/DFT reviews - Preparing comprehensive fabrication and assembly documentation (drawings, ODB++, drill files, stack-up tables, manufacturing notes) - Inspecting newly received PCBAs and participating in board-level manufacturing failure analysis - Contributing to reusable design constraints, layout workflows, and maintaining component-library assets (symbols, footprints, 3D models) Required qualifications: - 6+ years designing complex, multilayer PCBs - Fluency in Cadence Allegro PCB Designer and Constraint Manager - Strong HDI design experience (fine-pitch BGAs, microvias, blind/buried vias, via-in-pad, sequential lamination) - Understanding of signal and power integrity fundamentals (return paths, differential pairs, length matching, crosstalk, power delivery) - Experience working with PCB fabricators on stack-up development and manufacturing constraints - Strong cross-disciplinary communication skills Preferred qualifications include rigid-flex board experience, high-speed interface routing (PCIe, DDR, USB, Ethernet, MIPI), familiarity with SI/PI simulation tools (Cadence Sigrity, Ansys SIwave), power-electronics or mixed-signal layout experience, and knowledge of IPC standards or Cadence SKILL scripting. The role is based in San Francisco with an expectation of four days per week in-person presence.

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