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Xanadu is building quantum computers to solve the world's most challenging problems. The Low Temperature Devices team is seeking a Layout & Design Engineer to develop superconducting single-photon detector (SNSPD) components critical to Xanadu's fault-tolerant quantum architecture.
You will design and optimize complex multiplexed multi-pixel detector arrays, developing the internal process design kit (PDK) with a focus on advanced mask design for fabrication process optimization. This role bridges simulation and experiment by designing test structures and production tape-outs, leveraging Xanadu's partnerships with 300mm foundry processes and rapid 100mm in-house development capabilities.
Key responsibilities include capturing device layout requirements through collaboration with low-temperature device scientists, executing GDS mask layouts for test structures and production runs, performing device-level simulations, and developing automated pipelines to integrate design environments with simulation tools. You will regularly interact with the Fabrication Engineering team to align design strategies with fabrication capabilities, drive improvements in SNSPD performance metrics through layout optimization, and contribute to other simulation or computational projects aligned with your expertise.
Required qualifications: MSc or PhD in Engineering, Science, or related field with 2+ years of industrial experience. Expert-level experience with scripted photonic mask design/layout tools (gdsfactory, ipkiss3, Virtuoso, OptoDesigner, or similar). Expert-level knowledge of physical verification including DRC and LVS for manufacturing compliance. Experience generating GDSII/OAS layouts for MPW and dedicated mask sets. Proficiency with Git version control, Python for component design and simulation, and ability to work independently and collaboratively in fast-paced, cross-disciplinary environments.
Preferred qualifications include background in superconducting single-photon detectors, experience designing layouts for superconducting devices with understanding of operational principles, expertise in layout techniques accounting for fabrication effects (lithographic rounding, OPC/bias correction, material non-uniformity), and device-level simulation experience (e.g., COMSOL).
