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d-Matrix is seeking a Staff Analog Design Engineer to own the transmit and receive datapath of high-speed SerDes on their IO chiplet—the interconnect enabling their inference accelerators to scale beyond a single package. This is a hands-on, transistor-level design role where you will personally carry blocks from specification through silicon characterization on a small, collaborative team.
You will own transistor-level design of the SerDes transmit path, including output drivers (SST/CML), pre-driver and serializer stages, and transmit-side FFE. On the receive side, you will design the front-end (termination, ESD-aware input network, CTLE, VGA, samplers, and ADC-based architectures where applicable). You will design and verify the equalization path—DFE and FFE architecture, tap resolution, and adaptation behavior—and own the trade studies behind your architectural choices.
Key responsibilities include deriving block-level specifications from link budgets covering insertion loss, crosstalk, reflection, jitter, and BER targets; building comprehensive verification environments with testbenches, PVT corner coverage, six-sigma Monte Carlo, transient noise, and post-layout back-annotated simulation; performing link and channel modeling in MATLAB or Python; driving layout in deep sub-micron nodes with layout and package/signal-integrity engineers; and taking your blocks through silicon bring-up and bench characterization.
You will need a BS/MS/PhD in Electrical Engineering with 8+ years of hands-on analog and mixed-signal circuit design experience. Demonstrated ownership of a SerDes transmit or receive datapath block through to working silicon in a high-speed link is essential. You must have deep knowledge of high-speed driver design, receive front-end design, equalization, and practical familiarity with adjacent clocking and CDR blocks. Practical command of jitter and noise analysis, circuit design experience in advanced FinFET or GAA process nodes, and proficiency with industry-standard tools (Cadence Virtuoso, Spectre, MATLAB, Python) are required. Silicon bring-up and bench debug experience with high-speed lab equipment is critical.
Preferred qualifications include die-to-die interconnect experience (UCIe, BoW, proprietary D2D PHY), PAM4 signaling and DSP-based receiver architectures, familiarity with relevant specifications (UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7), experience porting datapath blocks across process nodes, IBIS-AMI model generation, SerDes ATE and production test development, and participation in standards bodies.
