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Ricursive Intelligence is a frontier AI lab building self-improving systems for chip design, closing the loop between AI and hardware to accelerate progress toward artificial superintelligence. As a Software Engineer on the Chip Design team, you will build the systems and infrastructure powering the end-to-end RTL-to-GDS flow—the complete pipeline from register-transfer level design through final layout and signoff.
You'll work across the design stack to improve how the company runs, evaluates, and iterates on complex chip designs at scale. Key responsibilities include developing and scaling infrastructure beyond monolithic scripts toward robust, hierarchical systems that support advanced process nodes and complex constraints; building reliable execution infrastructure for multi-stage design flows across different EDA (Electronic Design Automation) tools; connecting different stages of the flow with tooling that provides tight feedback loops; and analyzing design metrics like timing violations, congestion, and routing issues to help the flow converge faster toward better power, performance, and area (PPA) outcomes.
You'll also work alongside in-house chip design experts to productize cutting-edge algorithms into the production flow, deploy AI-driven methods to automate design analysis and optimization, and make engineering tradeoffs around quality, runtime, robustness, and deadlines. Your work will have direct impact on PPA in production chips—you'll debug issues that only emerge at scale and run against real designs with real constraints, not just academic benchmarks.
Minimum qualifications include a Bachelor's degree in Computer Science, Electrical Engineering, or related field; strong programming skills in Python, C++, Java, or comparable language; working understanding of the digital chip design flow from RTL through physical design and signoff; experience integrating, automating, or orchestrating EDA tools; and demonstrated ability to own ambiguous technical problems, ramp quickly in unfamiliar areas, and drive work to production.
Preferred qualifications include a Master's or PhD in a related field; experience with EDA, semiconductor design, distributed systems, or optimization; familiarity with design automation algorithms in placement, timing analysis, RC extraction, or netlist processing; and demonstrated quantified PPA benefits from AI/ML tooling such as AI-driven optimization, ML QoR prediction, or LLM-based flow automation.
