SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Lumilens is seeking a Senior Process Engineer to lead wafer bumping and fan-out process development for silicon photonic chips. This role owns the full lifecycle of advanced packaging process integration, from early-stage pathfinding through production support.
Key responsibilities include designing and optimizing wafer bumping and fan-out process flows, including thin-film sputtering, lithography, electroplating, and ball drop execution. You will conduct design-of-experiments (DOE) to characterize process windows and margins. Material characterization and qualification of new manufacturing inputs—dielectric photoresists, plating chemistries, underfills, and solder alloys—is a core function.
Reliability and stress engineering work includes designing DOE plans to characterize thermal and mechanical stress, and leading validation testing (Temperature Cycling Test, HAST, High-Temperature Storage). You will own root-cause diagnostics of structural failure modes unique to wafer-level chip-scale packaging (WLCSP), such as RDL cracking, ball bridging, bump missing, delamination, and wafer warpage. This includes hands-on use of SEM, CSAM, and physical cross-sectioning for failure analysis.
Process optimization focuses on key bumping parameters—wafer cleaning, UBM sputtering, solder ball plating, reflow, and bump inspection—to improve uniformity and yield. You will manage incoming wafer quality control, establish SPC control plans, and monitor process variation for long-term stability. Documentation responsibilities include process SOPs, work instructions, failure reports, and engineering change orders to support NPI and process verification.
Required: Bachelor's or Master's degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or equivalent. 5+ years of hands-on wafer bumping or fan-out process integration/development at an OSAT or IDM advanced packaging line. Deep practical understanding of photolithography, wet etching, CVD, and PVD. Comprehensive knowledge of finite element simulation for warpage, thermal dissipation, and structural integrity. Solid expertise with FMEA, SPC controls, and 8D problem-solving. High proficiency with JMP, Minitab, or Python. Experience with interposer, 2.5D/3D, or chip-on-wafer-on-substrate processes is advantageous.
