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Mythic is seeking a Rack-Scale AI Hardware Architect to own the complete design and implementation of rack-level reference architecture for AI compute systems. This is a senior individual-contributor role with significant technical scope and organizational influence.
You will own the full stack of rack-level design decisions, including:
**Architecture & Design Ownership**
- Board, chassis, backplane, rack topology, mechanical envelope, physical constraints, and serviceability from pathfinding through working reference implementation
- Scale-up and scale-out interconnect: PCIe hierarchy and switching, high-speed Ethernet and SerDes, die-to-die and board-level links, copper versus optical at each tier, retimers, connectors and cable plant, topology, oversubscription, and bandwidth/latency budgets
- Thermal architecture for high-density racks: direct-to-chip and cold-plate cooling versus immersion, CDUs and manifolds, flow and pressure budgets, component thermal limits, and rack-to-facility interface
- Power delivery architecture: rack distribution and busbar design, high-voltage DC and 48V-class conversion and efficiency, transient behavior across large device counts, redundancy, telemetry, and RAS
- Joint modeling with software teams of the full LLM solution, translating partitioning strategy, inter-layer traffic, and collectives into fabric, memory, and topology requirements backed by quantitative models
**Why This Matters**
Mythic's competitive advantage is energy per operation at the device level. Delivering that advantage at scale depends on the rack architecture—how it powers, cools, and moves data between a very large number of devices. At this density, the binding constraints are rack-level: fabric topology, connector and cable plant, power distribution, and thermal design. This role is where hardware and software architecture decisions converge, defining what an AI rack looks like when not built around traditional GPU trays.
**Success Metrics**
- A buildable rack reference implementation that meets performance, power, and thermal targets in hardware
- Coherent partitioning and fabric story enabling frontier-scale model mapping with appropriate interconnect provisioning
- Validated thermal and power architectures with measured data and headroom for next-generation devices
- Clear documentation enabling customer and partner deployment in real facilities
- Unified architecture across hardware, mechanical, and software teams
**Requirements**
- Minimum Bachelor's degree in Electrical Engineering, Mechanical Engineering, Computer Engineering, or related field, with relevant experience in server, datacenter, HPC, or AI system design
- Demonstrated architecture and design ownership of dense, rack-based server systems taken to production, including authoring specifications for ODM and OEM partners
- Expert command of state-of-the-art copper and optical interconnect: PCIe, high-speed Ethernet and SerDes, DAC and twinax, backplane and cabled channels, AOCs, and pluggable or co-packaged optics, with signal-integrity judgment
- Expert command of thermal architecture: cooling design, cold plates, manifolds, CDUs, flow and thermal budgeting, and facility-side interface
- Ability to reason across interconnect, power, thermal, mechanical, and software boundaries with a track record of modeling and trade studies driving architectural decisions
**Preferred Qualifications**
- Master's degree or PhD in Electrical Engineering, Mechanical Engineering, Computer Engineering, or related field
- Hyperscale or OCP experience, including ORv3 and contributions to relevant standards bodies
- Experience with systems built from many small accelerators, dataflow, or wafer-scale architectures
- Experience with LLM training or inference at scale and familiarity with chiplets, die-to-die interfaces, and advanced packaging
- Experience carrying reference designs through ODM or CM partners into production and customer datacenters, including EMC, structural, and shock/vibration qualification
