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Salary: USD 100,000 - 500,000 / annual
Tenstorrent is building cutting-edge AI technology and next-generation RISC-V CPU architectures with advanced chiplet solutions. The company is seeking an experienced Post-Silicon Lab Manager to own and scale the post-silicon lab infrastructure supporting bring-up, system validation, and customer enablement across multiple programs.
In this hybrid role based in Santa Clara, you will manage day-to-day lab operations for CPU post-silicon validation, power/performance assessment, and debug workflows. You will lead the lab environment for first-silicon power-on, system bring-up, and platform validation, including hands-on board-level fixes to salvage eval boards or meet new validation needs. You will deploy and maintain server racks, data acquisition systems, power telemetry rigs, and automated test benches for multi-core CPU and chiplet-based systems. You will manage the CapEx budget for test equipment including oscilloscopes, logic/protocol analyzers, and traffic generators.
Additional responsibilities include owning inventory management, calibration cycles, silicon allocation tracking, and lab safety compliance using JIRA, Confluence, and lab scheduling tools. You will direct post-silicon validation engineers to build cost-effective validation and debug infrastructure, and communicate clearly across functions to keep remote, multi-site teams aligned from the Santa Clara hub.
You will gain exposure to bringing up first silicon on advanced multi-core CPU and chiplet architectures, scaling a world-class post-silicon lab at a fast-moving company, debugging critical post-silicon issues alongside Emulation, Silicon Design, Software, and Architecture teams, and understanding how lab capacity planning and infrastructure decisions shape silicon schedules and product success.
**Requirements:**
- B.S. or M.S. in Electrical Engineering, Computer Engineering, or similar technical field
- 8–12+ years in semiconductor hardware
- 3+ years leading a post-silicon validation, characterization, or hardware lab team focused on CPUs
- Deep knowledge of high-speed interfaces (PCIe, DDR/GDDR/HBM, SerDes) and fabric links
- Hands-on experience with board-level debug tools
- Startup mindset with ability to stay calm and troubleshoot physical hardware under tight tape-out and silicon-arrival deadlines
- Strong cross-functional communication skills
