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Efficient Computer is developing ultra-low-power general-purpose processors using patented technology that consumes 100x less energy than state-of-the-art alternatives, enabling AI/ML to run continuously on AA batteries for 5-10 years. The company is seeking a Senior Physical Design Engineer to own end-to-end SOC top-level design for next-generation chips.
You will be the single point of ownership driving full-chip integration from block assembly through timing, power, signal integrity, and physical closure to tapeout-ready GDS. Key responsibilities include: full-chip floorplanning and power planning; timing closure across all corners and modes with multi-mode multi-corner STA; PDN design and IR-drop/EM analysis; physical verification (DRC/LVS/antenna); signal integrity and noise closure around high-speed IO and analog boundaries; clock and reset architecture; DFT integration including scan stitching and MBIST; package/IO co-design with bump mapping and IO ring planning; and tapeout readiness sign-off.
You will work closely with block-level physical design owners, DFT, package/IO teams, and architecture. This role sits in a newly formed hardware engineering group focused on state-of-the-art FinFET technologies. You'll mentor block-level PD engineers, set methodology standards, and serve as the technical leader and single point of contact for convergence tradeoffs across teams.
Required: Master's in EE with 5+ years industry experience (or PhD with 3+); 8-12+ years physical design experience with 2-3 full tapeouts at chip-top/SoC integration level; deep hands-on experience with advanced nodes; proven full-chip timing closure on complex SoCs; strong PDN/IR-drop/EM analysis (Voltus or equivalent); chip-level DFT integration experience; tool fluency in Innovus/ICC2, Tempus/PrimeTime, RedHawk, Calibre; ability to lead technically without direct reports; comfort with ownership and ambiguity in a fast-moving team; excellent TCL, shell, and Python scripting.
Desired: computer architecture knowledge, circuit design and device physics background, experience with non-standard architectures (dataflow, tiled, NoC-based), flip-chip/BGA package familiarity.
