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Mid Level ASIC Design Engineer

Tensordyne - Sunnyvale, CA, United States - In-office - posted 2026-08-05

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Tensordyne is a well-funded AI hardware startup designing high-performance, low-power AI inference accelerators for autonomous driving and other applications. The company has headquarters in Sunnyvale, CA and Munich, Germany, with a distributed team. As a Mid Level ASIC Design Engineer, you will be a core member of the ASIC design team responsible for the microarchitecture and RTL implementation of a convolutional neural network accelerator ASIC. This chip forms the foundation of the company's flagship perception module for autonomous driving, coupling novel computational accelerator units with third-party SoC IP blocks to achieve record-breaking performance at low power. Key responsibilities include: - Author and review microarchitecture specifications and test plans - Implement complex RTL designs in Verilog/SystemVerilog for multi-million gate ASICs - Integrate CPU and other IP blocks into the SoC subsystem - Collaborate with physical design and verification teams on implementation, timing closure, and power optimization - Analyze code coverage and provide feedback to verification engineers - Perform diagnostic and post-silicon validation testing, and assist with software bring-up Required qualifications: - 3+ years of ASIC design experience with demonstrable RTL logic design track record - Experience in IP integration, specifically CPU IP into SoC - Knowledge of ARM/RISC-V/MIPS architectures, memory hierarchy, cache coherency, virtual memory, and multicore CPU operation - Familiarity with AMBA/APB/AXI protocols and processor peripheral interfaces (SPI, eMMC, MII, GPIO, I2C) - Hands-on experience across the full ASIC development process with proficiency in front-end tools and methodologies - Familiarity with low-power design and UPF flow for multi-domain power intent - B.S. in Electrical or Computer Engineering (M.S. preferred) Preferred qualifications include timing closure experience at high frequencies and interest in AI architectures for convolution, transformer, and other workloads. The ideal candidate is a self-starter motivated to work in a dynamic startup environment.

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