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Great Sky is a technology startup developing neuroscience-inspired hardware and algorithms to overcome scaling challenges in AI systems. The company is building superconducting neural-network hardware that combines ultra-fast analog computation, local memory, and optical fan-out to enable inference with orders of magnitude speedups over current state-of-the-art systems.
You will serve as an Integrated Circuit Layout Engineer, optimizing superconducting electronic circuitry for Great Sky's AI hardware platform. Your primary focus will be creating and optimizing layouts for superconducting device cells, reusable circuit blocks, and larger hierarchical structures such as neural-network circuits. You will optimize these layouts for area, parasitics, device performance, manufacturability, and scaling.
Key responsibilities include:
- Creating layouts for individual superconducting device cells, reusable circuit blocks, and hierarchical neural-network circuits
- Optimizing layouts across multiple dimensions: area, parasitics, device performance, manufacturability, and scaling potential
- Extending and improving the parametric/script-based layout engine (Python-based) to enable rapid scaling to larger networks
- Supporting post-layout simulation and verification of passive and active superconducting circuits
- Collaborating with the fabrication team and external foundries to ensure successful chip manufacturing
In your first year, success means delivering verified layouts for key superconducting device cells and reusable circuit blocks, improving the reliability and scalability of the Python-based layout generation flow, and identifying and implementing meaningful area reductions in key device cells while preserving performance, manufacturability, and verification closure.
The company culture is onsite by default (founded by scientists accustomed to lab work), with flexibility for hybrid arrangements. For the right candidate and role, remote work is possible.
QUALIFICATIONS & REQUIREMENTS:
Required:
- Bachelor's degree in electrical engineering, computer engineering, physics, or related field, or equivalent practical experience
- 3+ years of experience in integrated circuit layout engineering in semiconductor or superconducting device domains
- Experience with IC layout tools and formats: Cadence Virtuoso, KLayout, Calibre, GDSII/OASIS, PCells, DRC/LVS, or similar workflows
- Strong scripting ability in Python or similar language, applied to parametric or automated layout generation
- Familiarity with post-layout extraction, parasitic-aware layout, or electromagnetic simulation workflows
- Direct contribution to at least one successful IC tapeout, preferably involving hierarchical layout, custom devices, or nonstandard process constraints
Preferred:
- Experience developing and customizing design rule check (DRC) procedures for integrated circuit layouts
- Experience building or maintaining parametric cells, layout generators, or scripted layout flows
- Experience with numerical analysis of superconducting circuits
- Experience managing large tapeouts with complex foundry processes
Note: Semiconductor IC layout experience is highly relevant; prior superconducting electronics experience is not required. The company will help you ramp on superconducting design rules, devices, and workflows.
