SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Ricursive Intelligence is a frontier AI lab building self-improving systems for chip design, closing the loop between AI and the hardware that powers it. We're reinventing chip development to recursively accelerate progress toward artificial superintelligence.
In this role, you will architect Ricursive's end-to-end RTL-to-GDSII physical design flow, spanning synthesis, DFT insertion, floorplanning, PDN design, placement, clock tree synthesis, routing, and comprehensive electrical and physical signoff. You'll own both top-down hierarchical planning (partitioning, pin/bump planning, timing/power budgets, abstraction generation) and bottom-up block closure that assembles cleanly at the chip level.
You will drive timing, power, and physical closure of the most complex, PPA-critical blocks in advanced nodes (5nm/3nm-class), managing multi-mode multi-corner convergence using industry-standard tools (PrimeTime/Tempus, RedHawk/Voltus, Calibre/Pegasus) through final ECOs and tapeout. A key part of this role is deploying and extending AI tooling across the flow—including AI-driven design-space optimization, ML-based PPA improvement, and LLM agents for run orchestration, log triage, constraint validation, and ECO generation—with measurable reductions in iteration count and time-to-closure.
You'll work closely with the research team to train and test self-improving design models and agents, defining quality metrics at every flow stage and encoding signoff-quality judgment into automated reward and checking infrastructure. You'll build the automation backbone in Python and Tcl: reproducible flow orchestration, regression and QoR-tracking dashboards, and correct-by-construction checks that make convergence visible and repeatable.
You'll partner with architecture, RTL, DFT, and foundry teams to structure designs for implementability and feed early physical feedback into microarchitecture and floorplan decisions. This is a small, early-stage team where methodology and infrastructure are still being defined—you will help shape them.
Required: BS in EE, CE, CS, or related field. 10+ years of hands-on physical design experience across the entire flow (synthesis, floorplanning, PDN, placement, CTS, routing, STA, extraction, power/EM/IR analysis, physical verification, LEC, ECO). Day-one fluency in production implementation and signoff stacks with commercial EDA tools, plus strong Tcl and Python scripting. Proven track record of successful chip design and tapeout, owning closure of complex blocks or full chips through complete signoff in advanced nodes on production silicon. Demonstrated quantified PPA benefits from AI/ML tooling in physical design.
Preferred: Master's or PhD in EE/CE/CS with VLSI or EDA focus. Deep expertise in high-performance compute silicon (ML accelerators, CPUs, GPUs, large SoCs), multi-voltage domain design, 2.5D/3D integration. Experience applying ML to chip design (RL-based placement, AI copilots, AI-for-EDA initiatives). Publications at major conferences (DAC, ICCAD, ISPD, DATE) in physical design or ML-for-EDA.
