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OpenAI's Forward Deployed Engineering team is seeking a Physical Design Engineer to serve as the subject matter expert for semiconductor customer engagements. This senior IC role combines deep physical design expertise with customer-facing technical advisory work, bridging frontier AI capabilities and real-world chip design workflows.
In the near term, you will be the team's physical design SME, helping Forward Deployed Engineers, Product, and Research teams understand backend implementation workflows, pressure-test AI-assisted solutions against real physical design constraints, and elevate the quality of customer-facing technical work. You'll build team fluency in implementation flows, EDA tooling, signoff methodology, and the trade-offs that shape physical design decisions.
Over time, the role expands into broader FDE ownership: partnering directly with semiconductor customers, shaping deployment strategy, building production-grade AI systems, driving technical workstreams, and turning high-touch deployments into repeatable solutions.
Key responsibilities include:
- Serve as physical design SME for customer engagements, advising on backend workflows, constraints, and opportunities
- Partner with FDEs during discovery to translate pain points into solution hypotheses and technical plans
- Support customer conversations as a trusted technical advisor
- Help shape AI-assisted solutions across floorplanning, place and route, clocking, timing closure, congestion, power, physical verification, and signoff
- Guide feasibility decisions across the entire chip design lifecycle
- Curate evaluation datasets, golden tasks, rubrics, and acceptance criteria for physical design use cases
- Build prototypes, benchmarks, and tools that validate opportunities
- Mentor the FDE team on physical design concepts and EDA tooling
- Surface customer signal to Product and Research to shape roadmap and platform capabilities
- Progressively take on broader FDE responsibilities including customer discovery and solution architecture
You bring 7+ years (BS) or 5+ years (MS) of hands-on physical design experience for complex ASIC or SoC programs, with demonstrated success bringing designs through tapeout. You have deep familiarity with industry-standard EDA tools and flows, strong understanding of how physical design intersects with microarchitecture and system-level trade-offs, and excellent communication skills. You're comfortable operating as a consultative expert, and you're excited to grow beyond domain expertise into broader solution building and customer-facing delivery.
