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Apple's silicon design group is seeking a Design Verification Engineer to ensure the quality and reliability of next-generation cellular baseband modems and transceiver link controllers. You'll be responsible for architecting and implementing highly reusable UVM-based verification environments that validate complex IP and subsystem designs for cellular systems powering millions of users worldwide.
Key responsibilities include constructing detailed test plans collaboratively with multi-functional teams, developing coverage-driven verification strategies from specifications, and architecting UVM-based test benches with stimulus generators, checkers, VIPs, and reference models. You'll implement test plans from RTL simulation through sign-off, debug failures, maintain regression suites, and report verification progress against coverage metrics. A significant aspect of this role involves leveraging Large Language Models (LLMs) and modern tools to enhance verification processes, designing ML-driven workflows that increase team productivity and verification quality.
The ideal candidate brings hands-on ASIC design verification experience using reusable methodologies like UVM, with strong proficiency in SystemVerilog, SystemC, C/C++, and Python/Perl. You should excel at test planning, constraint-random testing, SVA, and coverage-driven verification. Experience with 4G/5G cellular physical layer operation (3GPP), embedded processor core verification, and bus fabric architectures (AHB, AXI, NoC) is highly valued. Knowledge of prompt engineering and LLM workflow optimization is a plus.
This position offers exceptional opportunities to deepen expertise in cellular protocols, complex IP architectures, advanced fabric protocols, sophisticated debug methodologies, and best-in-class design verification practices including co-verification with models and firmware. You'll work on products that impact customers globally while advancing your technical expertise in high-performance cellular systems.
