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Efficient Computer is a fabless semiconductor startup developing energy-efficient general-purpose processors that use 100x less energy than state-of-the-art ultra-low-power alternatives. The company is seeking a Test Engineer to join the Operations team, serving as the primary interface between internal hardware engineering and external foundry, OSAT, and test partners.
In this mid-level role, you will own test engineering across multiple active chip programs, managing the full test lifecycle from DFT strategy through production. Key responsibilities include:
DFT Strategy & Pattern Development: Partner with design partners and internal engineers to define DFT strategy for each chip program. Generate, validate, and deliver ATPG patterns including scan, MBIST, JTAG, and embedded memory sequences. Develop and maintain STIL and PDL test program files. Drive DFT sign-off deliverables and resolve pattern-level issues. Support setup pattern generation including power-up/down sequences and test mode initialization. Define power rail sequencing requirements for safe ATE execution.
ATE Bringup & Test Program Development: Develop and debug test programs on Advantest and Teradyne platforms. Execute first silicon bringup on new tapeouts in partnership with hardware engineers and OSAT teams. Characterize device behavior across voltage, temperature, and frequency corners. Support load board bring-up and interface hardware validation. Define and manage test flows including wafer probe, final test, and bin sort. Optimize test time through pattern flow sequencing strategies.
OSAT & Supplier Coordination: Serve as primary test engineering interface with OSAT partners and test houses. Manage test program handoff including documentation, qualification, and acceptance criteria. Coordinate pattern delivery between design partners and OSAT. Track and analyze yield data, escalate anomalies, and drive corrective actions. Support die traceability and OTP programming flows. Coordinate with supply chain on test capacity planning.
Cross-Program Ownership: Own test engineering across multiple simultaneous chip programs. Build scalable test infrastructure and documentation for future programs. Contribute to DFT reviews, tapeout checklists, and test escape analysis. Help mature internal test engineering capabilities.
Required qualifications: 5+ years semiconductor test engineering in fabless or IDM environment. Hands-on DFT experience including scan insertion, ATPG, MBIST, and JTAG. STIL pattern generation and validation experience. ATE test program development on Advantest or Teradyne. OSAT/test house experience including wafer probe, final test, and load board bringup. Familiarity with power sequencing and DFT entry flows. Ability to coordinate with external design partners and OSAT suppliers across time zones. Strong written and verbal communication skills.
