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Etched is building purpose-built AI inference systems for transformers, delivering 10x higher performance and lower cost/latency than competing solutions. The company is developing custom ASICs that enable products impossible with GPUs, such as real-time video generation and deep chain-of-thought reasoning agents.
As a Substrate IC Package Layout Design Engineer, you will own the end-to-end design of complex IC substrate packages supporting high-power consumption and high-speed signaling. You will design large substrate packages (>50mm) with complex power delivery networks and high-speed signaling solutions up to 50GHz+. Working closely with silicon, signal integrity, power integrity, and system teams, you will co-design world-class substrates with OSAT providers, with intense focus on optimizing power delivery through the substrate.
Key responsibilities include:
- Leading design and development of complex IC substrate layouts for high-power AI processors and accelerators
- Designing large (>50mm) multi-layer substrate packages with high pin counts and dense routing requirements
- Ensuring robust power delivery designs supporting >700W custom silicon solutions
- Developing high-speed signal routing solutions for >50GHz signaling while minimizing signal integrity issues (loss, crosstalk)
- Collaborating with SI/PI engineers to define and implement signal integrity and power integrity requirements
- Optimizing CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance
- Working with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability
- Performing DRC and LVS verification for all substrate designs
- Developing and maintaining design documentation and guidelines
- Supporting design reviews and mentoring junior team members
Etched is a fully in-person team in San Jose and Taipei, valuing engineering skills highly with no boundaries between engineering and research. All technical staff contribute to both as needed.
REQUIREMENTS:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 10+ years of experience in IC substrate layout design for high-performance processors or accelerators
- Extensive experience with large substrate packages (>50mm) and complex high-density layouts
- Proven experience with high-power (700W+) package designs and robust power delivery networks
- Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches)
- Strong experience with CoWoS interposer design and understanding substrate design impact on CoWoS
- Advanced proficiency in Allegro Package Designer (constraint management, routing, design verification)
- Deep understanding of SI/PI principles and their application to package-level design
- Strong analytical skills and ability to work effectively in fast-paced, cross-functional team environment
