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Substrate IC Package Layout Design Engineer

Etched - San Jose, CA, United States - In-office - posted 2026-08-27

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Etched is building custom hardware for frontier AI inference, co-designing chips, racks, software, and manufacturing to optimize throughput and latency. As a Substrate IC Package Layout Design Engineer, you will own the end-to-end design of complex IC substrate packages supporting high-power consumption (700W+) and high-speed signaling (50GHz+). Key responsibilities include: - Lead design and development of complex IC substrate layouts for high-power AI processors and accelerators, including large (>50mm) multi-layer packages with high pin counts and dense routing. - Ensure robust power delivery designs capable of supporting >700W custom silicon solutions through substrate optimization. - Develop high-speed signal routing solutions (>50GHz) while minimizing signal integrity issues such as loss and crosstalk. - Collaborate with SI/PI engineers to define and implement signal integrity and power integrity requirements in substrate layout. - Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance. - Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability. - Perform DRC and LVS verification for all substrate designs. - Develop and maintain design documentation and guidelines for future substrate designs. - Support design reviews and provide technical guidance to junior team members. Ideal candidates have 10+ years of IC substrate layout design experience for high-performance processors, extensive expertise with large substrate packages and complex high-density layouts, proven experience with high-power package designs and robust power delivery networks, and advanced proficiency in Allegro Package Designer. Deep understanding of SI/PI principles at the package level and strong analytical skills in a fast-paced, cross-functional environment are essential. Etched is a fully in-person team in San Jose (Santana Row) that values engineering skills and expects technical staff to contribute across both engineering and research disciplines.

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