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Salary: USD 175,000 - 230,000 / annual
Quadric is building a revolutionary General Purpose Neural Processing Unit (GPNPU) that enables developers to run both neural network inference and conventional C++ code on a single programmable architecture. Founded by technologists from MIT and Carnegie Mellon, the company is a well-funded growth-stage semiconductor IP company powering intelligent edge devices across automotive, industrial, robotics, and embedded systems.
As a Staff SoC RTL Engineer, you will be a key member of the chip design team, contributing across all stages of the SoC design and integration cycle. You will help define the SoC architecture, own subsystem development, integrate third-party IP blocks, and drive PPA (Power, Performance, Area) optimization to bring the next-generation platform to life.
Key responsibilities include:
• Own SoC-level subsystem development and seamless integration with third-party IP such as NoC, PCIe/UCIe interfaces, DDR, and Security modules
• Contribute directly to SoC architecture definition by understanding application requirements
• Package designs for customer releases and iterate rapidly based on feedback
• Own Power, Performance, and Area optimization strategies at the SoC level
• Apply low-power digital design techniques to optimize hardware efficiency
• Drive timing closure across the full product lifecycle from front-end through back-end to tapeout
• Balance single-stream latency against scaled throughput performance
Within your first 6–12 months, you will independently own SoC subsystem development, drive measurable PPA improvements, develop deep understanding of the architecture and software interfaces to debug complex SW/HW stack issues, and successfully package and deliver design releases for customer evaluation.
Required qualifications: BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or related field; minimum 5+ years of hands-on SoC/ASIC front-end design and integration experience; proficiency in SystemVerilog or Verilog; strong background in computer architecture and low-power digital design techniques; deep technical knowledge in at least one subsystem (Memory, I/O, or Compute); proven experience with SoC subsystems including third-party IP; working knowledge of VCS and Verilog/C Co-Simulation.
Preferred: experience in logic synthesis and performance modeling, FPGA design, and familiarity with automotive safety standards (ASIL) and hardware security standards.
