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d-Matrix is seeking a Staff Analog Design Engineer to own the clocking subsystem of its high-speed SerDes on an IO chiplet. This is a hands-on, transistor-level role spanning PLL, DLL, phase interpolator, high-frequency clock distribution, and clock and data recovery (CDR) loop design. You will carry designs from specification through silicon characterization, working across porting proven blocks to new process nodes and ground-up design for next-generation links.
Key responsibilities include: transistor-level design of low-jitter frequency synthesis (LC and ring PLL, loop filter, charge pump, VCO, divider chain); phase interpolator and phase rotation scheme design with INL/DNL and glitch analysis; high-frequency clock distribution (buffer chains, duty-cycle correction, quadrature generation, skew control, supply isolation); CDR architecture definition and loop dynamics verification using MATLAB/Python with correlation to transistor-level and silicon results; phase-noise and jitter budgeting for the link; verification environment build-out (PSS/HB, transient noise, PVT corners, Monte Carlo, post-layout simulation); layout ownership in deep sub-micron nodes with focus on inductor/VCO layout, shielding, symmetry, and isolation; and silicon bring-up and bench characterization with correlation of measured to simulated results.
Required qualifications: BS/MS/PhD in Electrical Engineering with 5+ years hands-on analog and mixed-signal circuit design; demonstrated ownership of low-jitter PLL, phase interpolator, or CDR loop through silicon in high-speed SerDes; deep PLL architecture, loop dynamics, VCO design, and phase noise theory knowledge; practical jitter decomposition and budgeting experience; circuit design in advanced FinFET or GAA nodes using Cadence Virtuoso, Spectre, and standard methodologies; silicon bring-up and bench debug with phase noise analyzers, high-speed scopes, and BERTs.
Preferred: die-to-die interconnect experience (UCIe, BoW, proprietary D2D PHY); forwarded-clock and matched-source-synchronous architectures; digital and hybrid PLL/CDR implementations; familiarity with UCIe, OIF CEI-112G/224G, IEEE 802.3, PCIe Gen6/Gen7 specs; process node porting experience; standards body participation.
