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d-Matrix is seeking a Staff Analog Design Engineer to lead the migration of high-speed SerDes and mixed-signal blocks into new process nodes for their IO chiplet. This is a hands-on, high-impact role focused on process node migration—a design problem rather than a mechanical one—where you will own verification and characterization infrastructure that the analog team depends on.
Key responsibilities include:
- Owning the design migration of existing SerDes and mixed-signal blocks into new process nodes, including device mapping, re-sizing, bias/headroom re-budgeting, and re-verification against original specifications.
- Identifying architectural limitations that won't survive node changes and raising recommendations early.
- Building and maintaining analog verification infrastructure: testbench frameworks, regression setups, corner and Monte Carlo campaigns, and results management.
- Running post-layout back-annotated verification and collaborating with layout engineers on parasitic-driven issues.
- Generating and maintaining behavioral and Verilog-A models of analog blocks for full-chip verification, keeping them correlated with transistor-level design.
- Owning reliability and design-rule closure: electromigration, IR drop, ESD/latch-up compliance, and aging analysis.
- Contributing to testboard design and test feature definition, then running silicon characterization including bench setup, automation, and results correlation.
- Turning characterization results into actionable feedback loops for designers, future nodes, and product test/reliability teams.
Required qualifications:
- BS or MS in Electrical Engineering with 5+ years of hands-on analog or mixed-signal circuit design experience.
- Demonstrated ownership of analog/mixed-signal blocks through working silicon, including bench characterization and lab debugging.
- Direct experience migrating analog blocks between process nodes.
- Strong analog verification methodology with Cadence Virtuoso/Spectre/ADE fluency.
- Scripting proficiency in Python, SKILL, TCL, or equivalent.
Preferred qualifications include high-speed SerDes experience at 25 Gbps+, FinFET/GAA design at 7nm or below, die-to-die interconnect experience (UCIe, BoW), reliability analysis flows, Verilog-A modeling depth, ATE/production test development, and experience building reusable verification infrastructure.
