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d-Matrix is seeking a Senior Staff Power Performance Architect to own pre-silicon power estimation across next-generation AI accelerators. This is a central technical role that bridges architecture, RTL design, physical design, and silicon validation.
You will drive both RTL-level and physical-design-level power estimation, building an architectural power estimation tool that models power from system configuration and die-level metrics for AI workloads. You will partner closely with front-end architects, design verification engineers, and backend design teams to identify power activity windows, define performance monitoring requirements, and translate analysis into hardware capability improvements and die-level design changes.
Key responsibilities include:
- Own pre-silicon power estimation for design blocks across RTL and physical-design levels
- Partner with front-end and DV engineers to identify power activity windows and optimize power through RTL feedback
- Build an architectural power estimation tool for AI workloads that computes power from system configuration and die-level metrics, including workload profiling based on memory size, bandwidth, and gate counts
- Collaborate with frontend architects and backend design to define performance monitor availability and drive analysis into hardware improvements and design modifications
- Lead micro-architecture and RTL design, synthesis, and logic/physical power-performance verification using leading-edge CAD tools and semiconductor process technologies
- Design and implement performance-enabling and power-saving/monitoring functions; participate in silicon bring-up and validation
You will work in a culture emphasizing respect, collaboration, humility, and direct communication, with a team focused on execution and tackling complex challenges in generative AI hardware.
REQUIREMENTS:
- 8+ years of relevant experience in IC power/performance architecture, RTL, or physical design
- Master's degree in Electrical Engineering, Computer Engineering, or Computer Science
- Solid understanding of power, performance, micro-architecture, RTL, and physical design in digital systems and IC design, including the full IC design flow (Arch → uarch → RTL → Schematic → Layout → Verification → Fabrication → HVM)
- Familiarity with at least one EDA tool for power estimation
- Ability to move fluidly between RTL, physical design, and automation, including building script utilities to improve design execution productivity
- Programming proficiency in TCL and Python, with experience using libraries, APIs, data parsing, and algorithmic thinking
- Self-motivated with a fast, iterative approach to design work, sound engineering judgment, and a bias toward action
PREFERRED QUALIFICATIONS:
- Exposure to power estimation and performance metrics such as TDP, PMAX, EDP, Peak, and Average
- Familiarity with power/frequency scaling techniques (DFS, DVFS, AFS, AVFS)
- Familiarity with power delivery network (PDN) analysis, including resonance, impedance (Z(f)), and voltage droop analysis
