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Salary: USD 220,000 - 270,000 / annual
Lightmatter is a venture-backed company pioneering AI data center infrastructure through photonics technology. The company recently raised $400M in Series D funding at a $4.4B valuation and is scaling rapidly across all departments.
You will lead the physical design implementation of complex digital blocks for advanced process nodes (3nm and beyond), working on high-performance ASICs that integrate photonics with traditional silicon. This is a staff-level individual contributor role with significant technical scope and influence across the organization.
Key responsibilities include:
- Implement digital blocks from synthesis through physical verification using industry-standard EDA tools
- Drive full-chip static timing analysis (STA) signoff, constraint review, timing debug, and engineering change orders (ECOs)
- Conduct power analysis and optimization while balancing area and performance trade-offs
- Own full-chip floor planning, IO placement, and clock distribution strategies
- Customize clock implementation for functional and test modes
- Debug and resolve DRC/LVS violations
- Implement functional and timing ECOs
- Collaborate with EDA vendors on tool issues and flow optimization
- Write TCL, Python, or shell scripts to automate and customize design flows
You will work alongside world-class scientists and engineers tackling novel challenges at the intersection of photonics and semiconductor design—problems that are new to the industry.
Required qualifications:
- Bachelor's degree in Electrical Engineering or Computer Engineering
- 12+ years of industry experience as a Physical Design Engineer
- Proven track record completing block-level or top-level physical design for large ASICs or mixed-signal chips that successfully taped out
- Deep expertise in timing closure and LVS/DRC closure methodologies
- Proficiency in TCL and Python (or equivalent scripting languages)
- Strong collaboration and teamwork skills across functional teams
- Ability to thrive in a fast-paced, dynamic environment
Preferred qualifications:
- Master's degree in Electrical Engineering or Computer Engineering with 8+ years of industry experience
- Hands-on experience with Cadence design tools
- Tape-out experience on 3nm designs
- Willingness to perform manual layouts and learn silicon photonics layout techniques
- Experience with EM/IR analysis using industry-standard signoff tools
The role offers a hybrid work model with flexibility, competitive base salary, new-hire equity grants, annual performance-based equity, comprehensive health benefits, and professional development opportunities.
