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Salary: CAD 191,000 - 219,000 / annual
Lightmatter is a venture-backed company revolutionizing AI data center infrastructure through photonics technology. The company recently raised $400M in Series D funding at a $4.4B valuation and is scaling rapidly across all departments.
We are seeking a highly skilled Senior Physical Design Engineer to lead the implementation of complex digital blocks for advanced process nodes (3nm and beyond). This is a technical leadership role where you will drive critical aspects of ASIC design from synthesis through physical verification, working alongside world-class scientists and engineers on novel photonics-integrated systems.
Key Responsibilities:
- Implement and optimize digital blocks in advanced technology nodes using industry-standard EDA tools and flows
- Drive full-chip static timing analysis (STA) signoff, constraint review, timing closure, and engineering change order (ECO) implementation
- Lead power analysis and optimization while managing area and performance trade-offs
- Own full-chip floor planning, IO placement, and clock distribution strategies
- Customize clock implementations for functional and test modes
- Debug and resolve DRC/LVS violations to achieve clean physical verification
- Collaborate with EDA vendors to resolve tool issues and optimize flows
- Develop TCL, Python, and shell scripts to automate and customize design flows
Required Qualifications:
- Bachelor's degree in Electrical Engineering or Computer Engineering
- 12+ years of industry experience as a Physical Design Engineer
- Proven track record completing block-level or top-level physical design for large ASICs or mixed-signal chips that successfully taped out
- Deep expertise in timing closure, LVS/DRC closure, and physical verification methodologies
- Proficiency in TCL and Python (or equivalent scripting languages)
- Strong collaboration skills across cross-functional teams
- Ability to thrive in fast-paced, dynamic environments
Preferred Qualifications:
- Master's degree in Electrical or Computer Engineering with 8+ years of industry experience
- Hands-on experience with Cadence design tools
- Tape-out experience with 3nm process nodes
- Willingness to perform manual layouts and learn silicon photonics layout techniques
- Experience with EM/IR analysis using industry-standard signoff tools
This role offers competitive compensation, equity participation, comprehensive benefits including health coverage, retirement matching, flexible hybrid work arrangements, and professional development opportunities.
