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d-Matrix is seeking a Senior Staff PCB Design Engineer to lead the physical design of high-complexity AI accelerator boards and system baseboards. In this role, you will own full-cycle layout for ultra-high-density PCBAs (20+ layers) featuring 112G/224G SerDes signals and thousands of amps of power delivery. You will architect and manage the Constraint Manager hierarchy in Cadence Allegro, serving as the custodian of design methodology and driving automation, tooling, and constraint management processes that enable hardware development to scale with precision.
Key responsibilities include leading layout for PCIe form-factor AI accelerator cards and system baseboards, executing ultra-high-speed interfaces (PCIe Gen5/6, CXL, custom die-to-die interconnects), and partnering with power and ASIC teams on PDN strategy and multi-phase VRM layouts. You will develop automation scripts in SKILL, Python, or TCL to streamline layout tasks and DRC checks, define PCB stack-ups using advanced low-loss materials (Megtron 7/8), and serve as the primary interface with fabricators and contract manufacturers to ensure DFM, DFT, and DFA requirements for high-yield production.
You bring 10+ years of experience in high-speed, high-density PCB layout for servers, networking, or AI accelerators, with deep proficiency in Cadence Allegro Constraint Manager, high-speed routing techniques (back-drilling, via-in-pad, skip-vias), and complex DDR5/HBM interfaces. You have proven ability to write and deploy SKILL scripts or use Allegro's API, and understand PCB warpage mitigation for large-form-factor ASICs. Preferred qualifications include experience establishing Library Management Systems, PLM/PDM integration, and standardized footprint/padstack creation processes. A BS in Electrical or Electronic Engineering (or equivalent practical experience) is required.
