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Ambiq is a semiconductor company on a mission to enable intelligence everywhere by powering the AI edge revolution with the world's lowest-power chip solutions. Built on proprietary sub- and near-threshold technology, Ambiq's chips deliver multi-fold improvements in energy efficiency. Since 2010, the company has shipped over 300 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications.
You will own end-to-end digital verification of complex Systems-on-Chip (SoCs) integrating multiple CPUs, digital signal processors, security hardware, interconnects, and peripheral logic. As a self-starter, you will take full ownership of verification efforts and consistently deliver high-quality, production-ready silicon.
Key responsibilities include: developing detailed verification plans aligned with architecture and design specifications; performing block-level, sub-system, and full-chip SoC verification using simulation and regression environments; architecting and implementing scalable, reusable UVM-based testbenches in SystemVerilog; developing comprehensive test scenarios, stimulus, monitors, and checkers to achieve robust functional coverage; driving constrained-random and directed testing with scoreboarding and self-checking mechanisms; developing and maintaining C/C++ based verification libraries and tests for SoC-level validation; automating verification flows for regressions, coverage collection, and results reporting; defining, tracking, and closing functional and code coverage goals; utilizing advanced debugging methodologies to isolate and resolve complex design and verification issues; performing root-cause analysis and collaborating with design teams to drive fixes; and ensuring verification quality meets or exceeds project, schedule, and industry standards.
Required qualifications: BSEE or MSEE with 8–12 years of hands-on digital design verification experience; proven track record of multiple tape-outs with silicon functioning to specification; strong experience in block-level, sub-system, and full-chip SoC verification; ability to define and manage verification deliverables, milestones, and schedules; proactive identification of verification risks and implementation of mitigation strategies; experience working with complex SoCs integrating multiple 3rd-party IPs and VIPs; strong collaboration skills with design, architecture, and software teams; and excellent communication skills for reporting status, issues, and progress to stakeholders.
Technical skills required: SystemVerilog, UVM, Verilog, functional and code coverage methodologies, constrained-random verification and scoreboarding, C/C++ based verification in SoC environments, experience with processor-based systems (ARM and/or RISC-V preferred), AMBA protocols (AXI, AHB, APB), DMA, flow control, and standard serial interfaces. Experience with edge-based AI inference workloads is a plus.
