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Arago is an AI and computer hardware company founded in 2024 by AI researchers and physicists, focused on accelerating breakthroughs at the intersection of AI and semiconductors. The company operates from hubs in France, North America, and Israel with a lean, multinational team of engineers and scientists from top companies and research labs.
As a Performance Software Engineer, you will develop core computation software for Arago's custom AI accelerators. This role bridges host systems and proprietary hardware, encompassing custom on-board kernels, real-time debugging tooling, chip bring-up, and high-performance computation primitives. You will ensure the architecture operates with maximum efficiency and deterministic performance.
Key responsibilities include developing and optimizing low-level software primitives in C/C++, assembly, and architecture-specific intrinsics for RISC-V and ARM platforms. You will implement performance-critical kernels, runtime components, hardware abstraction layers, drivers, and firmware in bare-metal or highly constrained environments. Close collaboration with hardware architects and RTL/design teams is essential to define and validate hardware-software interfaces, memory maps, register interfaces, interrupts, synchronization mechanisms, and boot flows.
You will analyze and optimize software for latency, throughput, memory footprint, instruction count, and efficient processor/accelerator feature utilization. Responsibilities include bringing up and debugging software on simulation, emulation, FPGA, and silicon platforms, addressing low-level hardware/software integration issues. You will develop validation tests, benchmarks, and diagnostic tools for new processor, DSP, accelerator, and SoC functionality, and contribute to architecture decisions around ISA extensions, compiler intrinsics, memory hierarchy, DMA, cache/coherency behavior, and software-visible hardware features.
Required qualifications include a Bachelor's, Master's, or PhD in Computer Science, Computer Engineering, or related field. Strong experience in low-level systems programming with C/C++ and assembly is essential, with excellent understanding of how compiled software maps to machine instructions and hardware behavior. Deep familiarity with bare-metal development (startup code, linker scripts, memory layout, MMIO, interrupts/exceptions, timers, synchronization, peripheral access) is required. You must have strong understanding of computer architecture including pipelines, caches, memory hierarchies, virtual/physical addressing, atomics, DMA, and performance implications of access patterns. Hands-on experience with RISC-V and/or ARM architectures, instruction sets, calling conventions, ABI concepts, and architecture-specific intrinsics is necessary. Experience debugging hardware/software interactions using GDB, JTAG, trace/debug interfaces, simulators, emulators, or FPGA platforms is required. Ability to read hardware specifications, register descriptions, and RTL-level documentation and translate them into robust software implementations is essential. Strong performance-analysis and optimization skills including profiling, disassembly inspection, compiler optimization behavior, and hand-tuned assembly are required. Proficient English is mandatory; French is a plus.
