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Graphcore is building next-generation AI compute infrastructure as part of the SoftBank Group. The Physical Design team is responsible for creating high-quality silicon layouts for advanced AI superchips, working across the complete design stack from RTL through final GDSII sign-off at leading-edge process nodes (7nm and below).
In this role, you will contribute technically to the development of Graphcore's next-generation AI chips, focusing on robust, high-performance, and power-efficient designs while meeting aggressive schedules. You will use state-of-the-art EDA tools and Graphcore's proprietary flows to deliver sign-off-quality designs. Responsibilities span multiple areas: delivering final designs using advanced EDA tools and in-house flows; enhancing existing flows and tools to support new features and methodologies; analyzing and debugging complex engineering problems to develop workable solutions; and developing understanding of emerging technical issues to optimize flows and methodologies.
You will work closely with other teams within Graphcore (RTL, verification, DFT, architecture, packaging, product engineering) and with third-party support engineers and contractors. The physical design team is not siloed; engineers are trusted to take ownership of their designs and encouraged to drive improvements across all aspects of the work.
Essential qualifications include a degree in Electronic/Electrical Engineering, Computer Science, or related field; strong motivation and self-starter mentality; excellent problem-solving and debugging skills; programming/scripting ability (Tcl and Python); hands-on experience with 7nm or smaller technologies; and broad experience across physical design flows including floorplanning, synthesis, place and route, clock tree synthesis, timing analysis, logical equivalence checking, and physical verification (DRC/LVS/ERC).
Desirable experience includes deep expertise in specific physical design areas, PPA optimization, silicon transistor knowledge, 2D/3D design (CoWoS, UCIe), high-speed/high-power chip design, advanced interface protocols (Ethernet, PCIe, LPDDR, HBM), power integrity optimization, 2nm/3nm process experience, chip finishing, design for test, team management, and project planning.
