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OLIX is building next-generation AI accelerators to address the infrastructure gap created by explosive AI demand. The company is architecting the Decode Accelerator 1 (DX-1), a specialized chip that combines logic, data movement, packaging, optics, and interconnect at rack scale for breakthrough performance in AI workloads.
As a Senior Design for Test (DFT) Engineer, you will own the end-to-end DFT strategy and implementation for complex, high-performance digital pipelines in advanced CMOS nodes. This is a hands-on technical role with significant scope and mentorship responsibilities.
Key responsibilities include:
- Architecting comprehensive DFT strategies for high-throughput digital designs, ensuring high test coverage and efficient test execution
- Leading integration and verification of advanced DFT features (Scan, JTAG, Boundary Scan, Memory BIST) to industrial standards
- Partnering with test engineering to develop and optimize ATE-compatible test patterns (stuck-at, transition, bridging) for aggressive fault coverage and manufacturing yield
- Driving RTL development in SystemVerilog/Verilog/VHDL with focus on DFT architecture, synthesis constraints, and formal/constrained-random verification
- Analyzing and minimizing DFT impact on power, performance, and area (PPA) through innovative test access techniques
- Collaborating with mixed-signal and software teams on DFT interfaces, test modes, and firmware abstractions
- Mentoring junior engineers, leading design reviews, and championing DFT best practices across the ASIC lifecycle
Required experience: 7+ years hands-on DFT architecture and implementation for high-performance ASICs/SoCs, with proven ownership of at least one product featuring comprehensive DFT coverage. Must have expertise in advanced DFT features on multi-hundred-MHz to multi-GHz designs, industry-standard EDA flows (Scan insertion, ATPG, pattern simulation, fault modeling), and DFT-specific techniques (compression, EDT, JTAG/IEEE 1149.1/1687). Strong proficiency with Python/Tcl scripting for automation and debug, solid semiconductor physics knowledge, and excellent cross-functional collaboration skills required.
Nice-to-have qualifications include tape-out experience at 22nm or below, high-speed SerDes or HBM/DDR DFT expertise, familiarity with AI/ML workloads and systolic arrays, and open-source DFT tool contributions.
Compensation includes competitive salary commensurate with experience, meaningful equity/stock options, an annual living-local bonus for proximity to the Bristol office, and employer-contributed retirement benefits.
