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Graphcore is a globally recognized leader in AI computing systems, designing advanced semiconductors and data center hardware that power AI innovation. As part of the SoftBank Group, the company develops specialized processors for AI workloads.
The Senior Silicon Logical Design Engineer will work within the logical design team, responsible for delivering microarchitecture and RTL (Register Transfer Level) design to implement Graphcore's chip architecture specifications. This role involves close collaboration with other silicon engineers to ensure high-quality chip delivery and meet company objectives.
Key responsibilities include:
- Integrating IP blocks and subsystems into top-level SoC (System-on-Chip) designs
- Developing and maintaining build and configuration environments
- Performing synthesis, linting, CDC/RDC (Clock Domain Crossing/Reset Domain Crossing), and timing checks at the SoC level
- Supporting verification and physical design teams through clean interface hand-offs
- Debugging and resolving integration-related issues across multiple design hierarchies
- Contributing to continuous improvement of integration flows and automation
- Producing high-quality microarchitecture documentation
- Ensuring consistent communication and working practices across distributed teams
Required qualifications:
- 4-8 years of experience in logical design within the semiconductor industry or product development
- Degree in Computer Science, Engineering, or related field
- Proficiency in SystemVerilog and digital design flows
- Scripting ability in Python and/or TCL for automation
- Strong debugging and root-cause analysis skills
- Self-motivated, collaborative team player
Desirable experience includes processor design, application-specific blocks, high-speed serial interfaces, complex IP integration, arithmetic pipeline design, floating-point design, design for test, synthesis, timing analysis, project planning, power integrity, and silicon transistor knowledge.
