SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Nexthop AI is seeking an experienced Senior Signal Integrity Engineer to own high-speed channel design for next-generation switch platforms operating at 224G PAM4 and beyond. This is a platform ownership role spanning concept through production bring-up and debug.
You will be the signal integrity owner for one or more switch platforms, responsible for end-to-end SI from pre-layout feasibility through EVT/DVT link bring-up. Key responsibilities include:
- Setting channel targets and loss budgets for 224G PAM4 per lane and beyond, balancing ASIC SerDes capability, module requirements, cost, and manufacturability
- Driving complex interconnect problems: ASIC BGA escape design, connector launch optimization, via tuning at high frequencies, sequential lamination and backdrill strategy, and cascade behavior across the full channel
- Owning stackup and material strategy with PCB fab vendors, including laminate selection, Dk/Df modeling, impedance and loss coupon coverage, and DFM closure
- Running compliance and link analysis (COM, ERL, IEEE 802.3dj metrics) for C2M and C2C channels across the module ecosystem
- Leading correlation between simulation, coupon data, and system measurement using VNA, TDR, high-speed scopes, BERT, and ASIC SerDes diagnostics
- Working directly with ASIC, connector, and package vendors on models, launch geometry, and specifications
- Improving team processes through simulation automation in Python, reusable analysis flows, and SI design rules
- Mentoring junior SI engineers, reviewing their analysis, and participating in hiring
The role requires regular onsite presence in the Bay Area office for hands-on lab correlation and bring-up work. You'll be working on products built for the largest AI deployments in the world, solving interconnect problems at the edge of what copper can deliver.
REQUIREMENTS:
- MS or PhD in Electrical Engineering, Physics, or related field (BS with equivalent depth considered)
- 10-15 years of signal integrity experience on high-speed system design
- Proven track record owning SI for complex boards through production, ideally high pin-count, high-power ASIC designs at 50G/lane or above
- Deep expertise in 3D EM simulation and extraction (HFSS, SIwave, Sigrity, ADS, or equivalent) with model correlation to measurement
- Command of differential and mixed-mode S-parameters, mode conversion, crosstalk attribution, and time-domain analysis
- Experience with link budgeting and compliance methodology for high-speed Ethernet (COM, ERL, IEEE 802.3ck/802.3dj or comparable), including C2M channel definition
- Hands-on knowledge of PCB stackup design, low-loss materials, and fabrication process capability
- Strong Python skills for simulation automation and large-scale data analysis
- Hands-on skills in via and launch structure design validation against measured data, high-speed measurement and de-embedding, and critical layout review
NICE TO HAVE:
- 224G PAM4 / 200G-per-lane channel design experience
- Participation in IEEE 802.3 or OIF standards work
- Experience with cabled and optical module ecosystems (OSFP, QSFP-DD, DAC/ACC/AEC/LPO/LRO)
- Power integrity or EMC breadth alongside SI
- Experience building an SI methodology or team from early stage
