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Salary: USD 124,000 - 186,000 / annual
IonQ is the world's leading quantum computing platform and merchant supplier, delivering integrated quantum solutions across computing, networking, sensing, and security. The company achieved 99.99% two-qubit gate fidelity in 2025, setting a world record in quantum computing performance. IonQ's systems are used by customers including Amazon Web Services and AstraZeneca for drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense.
You will join the Processor Design team at Oxford Ionics (now part of IonQ) as a Senior QPU Design Engineer. Your mission is to integrate all features required to operate quantum computers into complex chips, advancing the design of high-performance quantum processing units. You will work closely with scientists and fabrication engineers to bring new ion-trapping chip designs into production.
Key responsibilities include:
- Guiding chips through the complete design process, from requirements to layout and tape-out
- Laying out complex multi-layer chips, including metal-track routing and interfaces with photonics and CMOS
- Collaborating with scientists to understand their requirements and establish specifications
- Coordinating with other teams to ensure feasibility and compatibility
- Taking charge of projects independently and owning delivery of the final tape-out
- Turning operational requirements into chip layout to enable new quantum technologies
You will expand the range of features supported by chips, contributing directly to building utility-scale quantum computers. This is a hands-on role where you will drive the design process, solve problems as they arise, and take responsibility for delivery within a fast-moving, highly technical team.
REQUIREMENTS:
- Experience translating design requirements into features
- Hands-on experience in chip layout
- Ability to work across teams and discuss multiple aspects of chip design
- Understanding of how different chip components influence and constrain one another
- Capability to take on layout work independently
- Preferred: Experience with scripted layout generation using GDSFactory in Python or similar
- Preferred: Experience using Cadence for IC layout
- Preferred: Experience in ion trap design, photonics design, or IC packaging
