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Arago is re-engineering computing from first principles by fusing optical and CMOS technologies to deliver order-of-magnitude performance gains for AI workloads. The company has built the fastest processor of its kind and is backed by leading deep-tech investors and industry luminaries including the CEO of Arm, the founder of macOS, an Nvidia Fellow, and Google's Head of Optics.
As Senior Mixed-Signal Verification Engineer, you will own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago's Systems-on-Chip. You will work across analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.
Key responsibilities include: owning the mixed-signal verification methodology and verification plan for digital-to-analog interfaces; building and maintaining verification environments at block, subsystem, and SoC level; developing tests, assertions, checkers, scoreboards, and functional coverage; verifying digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions; running regressions, analyzing coverage, debugging failures, and driving verification to sign-off; developing or integrating behavioral and real-number models for efficient mixed-signal simulation; and collaborating closely with analog, RTL, architecture, firmware, and SoC verification teams.
Required qualifications: strong hands-on ASIC or SoC verification experience; experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces; strong SystemVerilog skills and practical UVM or equivalent methodology experience; experience building verification environments and developing tests, assertions, scoreboards, and functional coverage; good understanding of digital design fundamentals and basic analog/mixed-signal concepts; strong debugging skills spanning RTL, models, clocks, resets, configuration, and analog behavior; experience with scripting and automation (Python, Tcl, shell, or similar); proficient English.
Nice-to-have skills include verification experience with complex high-speed interface IP (PCIe, DDR/LPDDR, UCIe, SerDes, USB, CXL), interface initialization and link training, real-number modeling techniques, behavioral model development, SoC-level integration, low-power verification, and experience driving complex IP or SoC verification through coverage closure and tape-out.
Compensation includes competitive cash compensation based on location and experience, meaningful stock options, healthcare coverage with family-friendly options, pension contributions, professional development support, and 25 days PTO plus public holidays. The role offers ownership of a key technical domain with significant growth opportunities.
