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Arago is an AI and computer hardware company founded in 2024 by AI researchers and physicists, focused on accelerating breakthroughs at the intersection of AI and semiconductors. The company operates from hubs in France, North America, and Israel, with a lean, multicultural team (nine nationalities) drawn from top companies and research labs. Backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent deeptech venture firms, Arago is building custom tensor units and advanced computation platforms for AI/ML applications.
In this role, you will design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads. You'll work on Arago's custom multiphysics computation unit, collaborating closely with system software and architecture teams.
Key responsibilities include:
- Design, implement, and verify RTL blocks for memory, control, and compute subsystems
- Collaborate with system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals
- Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches
- Support synthesis, timing analysis, and backend integration with physical design and CAD engineers
- Contribute to architectural exploration and hardware-software co-design efforts for future compute platform iterations
The company values great science, high velocity, and strong team relationships grounded in trust and camaraderie. You'll have ownership of key technical domains with significant growth opportunities.
REQUIREMENTS:
- Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units
- Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration
- Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus)
- Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT
- Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support
- English at a proficient level; French is a plus
