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Senior FPGA Verification Engineer, Air Dominance and Strike

Anduril - Costa Mesa, CA, United States - In-office - posted 2026-09-02

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Salary: USD 166,000 - 220,000 / annual

Anduril Industries is seeking a Senior FPGA Verification Engineer to join the Air Dominance and Strike team in Costa Mesa, CA. You will own the verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics systems, with a focus on UVM-based methodology and coverage-driven verification. Key responsibilities include architecting and implementing UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD Xilinx FPGA/SoC designs. You will develop comprehensive verification plans with traceability to system and hardware requirements, author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks, and build functional coverage models while driving code coverage analysis to closure. You will develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs, establish and maintain regression suites tracking coverage metrics and verification progress, and debug failures using waveform tools and simulation logs at both HDL and system levels. Collaboration with design engineers on RTL reviews, bug resolution, and micro-architecture refinement is essential. Additional duties include supporting hardware validation and board bring-up on target platforms, ensuring verification meets DO-254 and relevant safety standards, and authoring verification closure reports and coverage analysis summaries. Required qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; 8+ years of FPGA/ASIC verification experience; proficiency in SystemVerilog, UVM methodology, and SVA; object-oriented programming principles; experience with industry simulators (Questa, VCS, Xcelium, Vivado); Git-based collaborative workflows; Linux development environments; strong communication and teamwork skills; and eligibility to obtain and hold a U.S. Secret security clearance. Preferred qualifications include 12+ years of verification experience, Master's degree, DO-254 and avionics verification standards knowledge, formal verification tools, digital interface expertise (Ethernet, PCIe, JESD204C, MIL-STD-1553, SPI), verification automation scripting (Python, Tcl, Makefile), SoC and ARM-based embedded platforms, and CI/CD integration experience.

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