SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 184,000 - 208,000 / annual
Muon Space, a LEO satellite constellation provider founded in 2021, is seeking a Senior FPGA Engineer to design the network fabric and security architecture for next-generation spacecraft. This is a hands-on role with significant architectural influence, requiring you to define onboard networking concepts, write RTL, and collaborate closely with the Staff Architect, electrical engineering team, and payload engineers.
Key responsibilities include:
- Defining onboard networking architecture (switching, routing, packet filtering, firewalling, deep packet inspection, VPN)
- Designing and implementing end-to-end encryption, packet-based encryption at router level, and file-based encryption for onboard and downlink data
- Driving the definition of an onboard Ethernet switching/routing device and evaluating implementation options (COTS, semi-custom, fully custom FPGA)
- Designing and building a spacecraft Network-on-Chip (NoC) and robust FPGA-to-FPGA links with continuous health monitoring
- Owning Ethernet PHY and MAC integration on FPGAs, link aggregation, and signal-integrity trade-offs
- Applying FEC schemes (e.g., Reed-Solomon) to onboard and inter-FPGA links
- Integrating the network fabric with customer payloads for interoperability and validation
- Publishing white papers on Muon's networking and security solutions
- Collaborating with the Staff Onboard Compute Architect to harmonize networking and security into the broader compute architecture
Required qualifications: Bachelor's or Master's degree in Computer Science, Computer Engineering, Electrical Engineering, or related field, plus 5+ years of professional FPGA engineering experience with specialization in networking, cryptography, security, or high-speed I/O. Deep hands-on experience with Ethernet, link aggregation, and signal-integrity at higher DAC lane rates. Strong practical experience applying cryptographic algorithms in hardware (AES, AES-GCM, ECC, IPSec/VPN, post-quantum cryptography). Working knowledge of FEC schemes, particularly Reed-Solomon. Proven experience defining network packet flows, switching/routing/filtering, deep packet inspection, firewalling, and VPN termination in embedded or FPGA systems. Strong HDL/RTL skills (SystemVerilog, Verilog, VHDL) and familiarity with modern FPGA verification methodologies. Excellent written and verbal communication skills. Ability and willingness to obtain and maintain a U.S. security clearance (active clearance is a plus).
Nice-to-have skills include experience with spacecraft networks (Ethernet, SpaceWire), NoC fabric implementation/integration, space-grade or rad-tolerant FPGA platforms, prior spacecraft avionics/payload data handling work, and contributions to standards bodies or open-source cryptographic implementations.
