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Salary: USD 166,000 - 220,000 / annual
Anduril Industries is a defense technology company transforming U.S. and allied military capabilities through advanced technology. The Cyber business line is a new division focused on enabling offensive cyber missions by leveraging Anduril's fleet of autonomous vehicles, Lattice OS (an AI-powered operating system), mesh networks, and hardware products to conduct cyber operations at the edge.
The Senior FPGA Engineer will design and implement high-throughput FPGA datapaths, packetization pipelines, timing-sensitive interfaces, and hardware-near acceleration blocks. Key responsibilities include owning RTL design, simulation, verification, and lab bring-up across VHDL, Verilog, or SystemVerilog-based workflows. The engineer will work closely with DSP, software, hardware, and systems engineers to translate algorithm and interface requirements into robust FPGA implementations, drive precision timing and synchronization closure, and document architectures for cross-functional integration and maintainability.
Required qualifications include strong FPGA development experience on Xilinx or comparable platforms (SoC/MPSoC-based or high-performance digital devices relevant to SDR systems), proficiency in VHDL/Verilog/SystemVerilog with simulation and timing closure expertise, hands-on experience building high-speed digital interfaces (Ethernet-based packet movement, DMA flows, streaming signal pipelines), familiarity with precision timing and deterministic interface behavior, FPGA verification methodologies and automation, ability to collaborate with software and DSP engineers on register interfaces and integration boundaries, and lab debugging skills using oscilloscopes, logic analyzers, and spectrum analyzers.
Preferred qualifications include experience with cocotb, GitLab CI/CD, FFT/channelization pipelines, signal-processing FPGA implementations, embedded software interfaces to FPGA systems (Linux-based control planes), customer-facing design reviews, and mentoring other engineers on FPGA/DSP teams.
