SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Quadric is a growth-stage semiconductor IP company building the industry's first General Purpose Neural Processing Unit (GPNPU) for edge AI applications. Founded by technologists from MIT and Carnegie Mellon, the company enables developers to run neural network inference and conventional C++ code on a single programmable architecture, powering intelligent edge devices across automotive, industrial, robotics, and embedded systems.
As Senior Design Verification Engineer, you will take technical leadership in architecting and building the SoC-level verification environment from the ground floor. You'll collaborate closely with architects, hardware engineers, and software teams to ensure high-quality verification coverage for next-generation GPNPU-based SoCs.
Key responsibilities include:
**Testbench Architecture & Test Plan Development**
- Architect and build novel, scratch-built testbenches for SoC-level verification of GPNPU-based SoCs
- Collaborate cross-functionally to document comprehensive verification test plans
- Implement scalable testbenches using commercial Verification IP (VIP) and internal software utilities
**Test Execution & Verification Coverage**
- Develop directed and random drivers, assembly, and C++ programs to stress-test SoC subsystems and integration
- Verify complex SoC subsystems including 3rd-party IP (NoC, PCIe/UCIe, DDR)
- Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting
- Track, analyze, and communicate verification progress using functional and code coverage metrics
**Success Metrics (6-12 months)**
- Deploy a fully functional, scratch-built SoC-level UVM verification environment
- Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks
- Establish robust co-simulation pipelines validating HW/SW execution before tapeout
**Required Qualifications**
- Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs
- Deep expertise in UVM methodology and SoC-level verification practices
- Proficiency in SystemVerilog or Verilog, assembly programming, and Python
- Hands-on experience verifying SoC subsystems and 3rd-party IP
- Strong computer architecture background with VCS and Verilog/C Co-Simulation experience
Quadric offers competitive salary, equity, medical/dental/vision insurance, paid parental leave, PF retirement plan, flexible PTO, and a collaborative culture with significant ownership and impact.
