SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 180,000 - 260,000 / annual
K2 Space is seeking a Senior ASIC Package Design Engineer to lead advanced ASIC package architecture development for high-performance satellites. The company is building the largest and highest-power satellites ever flown, backed by over $1 billion in funding and $1 billion in signed contracts across commercial and US government customers. With multiple launches planned for 2027 and scaling to 100 satellites per year, this role is critical to K2's mission.
You will implement end-to-end package strategy for high-performance mixed-signal and digital SoCs, from early architecture and trade studies through vendor engagement, qualification, and production ramp. Your focus will be on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions for complex, high-speed, power-dense ASICs.
Key responsibilities include:
- Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints
- Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability
- Establish package design standards, methodologies, and best practices
- Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content
- Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning
- Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces
- Support package-level SI/PI strategy, including high-speed digital interfaces and power delivery network (PDN) design
- Lead thermal architecture at the package level, including lid selection, thermal interface materials (TIMs), heat-spreaders, and mechanical interfaces to system cooling
- Manage relationships with external packaging vendors, substrate suppliers, and OSATs (outsourced semiconductor assembly and test providers)
- Drive material selection, substrate technology choices, and assembly process optimization
You will collaborate with internal teams to define standards, influence silicon and system architecture, and ensure first-pass success for complex ASICs destined for the harshest radiation environments.
REQUIREMENTS:
- Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or related field
- 5+ years of experience in ASIC package design with deep expertise in FC-BGA
- Proven experience delivering high-pin-count, high-performance ASIC packages into production
- Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs
- Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS
- Experience working directly with OSATs and substrate vendors
- Knowledge of packaging qualification and test methodologies
NICE TO HAVE:
- Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates)
- Background in high-speed digital or mixed-signal SoCs
- Familiarity with aerospace, space, or high-reliability electronics
NOTE: This role requires U.S. Person status or eligibility for a federally issued export control license due to ITAR compliance.
