SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Salary: USD 180,000 - 260,000 / annual
K2 Space is building the largest and highest-power satellites ever flown, backed by over $1 billion in total funding and $1 billion in signed contracts across commercial and US government customers. The company is mass-producing high-power satellite platforms for missions from LEO to deep space, with multiple launches planned for 2027 and scaling to 100 satellites per year.
You will serve as Senior ASIC Package Design Engineer, responsible for implementing advanced ASIC package architecture with a strong focus on flip-chip BGA (FC-BGA) and multi-chip module (MCM) solutions. This role supports end-to-end package strategy for high-performance mixed-signal and digital SoCs from early architecture and trade studies through vendor engagement, qualification, and production ramp.
Key responsibilities include:
- Define ASIC package architecture for FC-BGA and MCM solutions, including substrate stack-up, ball-map strategy, power delivery, signal breakout, and mechanical constraints
- Lead package-level trade studies across cost, performance, power integrity (PI), signal integrity (SI), thermal, manufacturability, and reliability
- Establish package design standards, methodologies, and best practices
- Drive detailed design of FC-BGA packages for high-pin-count ASICs with high-speed SerDes, dense power grids, and RF signal content
- Define and review substrate stack-ups, via strategies, impedance control, escape routing, and reference plane planning
- Partner with silicon, RF, and systems teams to co-optimize die floorplans and package interfaces
- Support package-level SI/PI strategy, including high-speed digital interfaces and power delivery network (PDN) design
- Lead thermal architecture at the package level, including lid selection, TIMs, heat-spreaders, and mechanical interfaces to system cooling
- Manage relationships with external packaging vendors, substrate suppliers, and OSATs
- Drive material selection, substrate technology choices, and assembly process optimization
You will collaborate with internal teams to define standards, influence silicon and system architecture, and ensure first-pass success for complex, high-speed, power-dense ASICs.
REQUIREMENTS:
- Bachelor's degree in Packaging Engineering, Mechanical Engineering, Electrical Engineering, or related field
- 5+ years of experience in ASIC package design with deep expertise in FC-BGA
- Proven experience delivering high-pin-count, high-performance ASIC packages into production
- Strong understanding of substrate technologies and materials, SI/PI fundamentals at the package level, and thermal management for power-dense ASICs
- Fluent in SI/PI and EM simulation tools such as SIWave, HFSS, and ADS
- Experience working directly with OSATs and substrate vendors
- Knowledge of packaging qualification and test methodologies
NICE TO HAVE:
- Experience with MCM or heterogeneous integration (chiplets, interposers, advanced laminates)
- Background in high-speed digital or mixed-signal SoCs
- Familiarity with aerospace, space, or high-reliability electronics
Note: ITAR compliance required. Must be a U.S. Person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
