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K2 Space is building the largest and highest-power satellites ever flown, backed by $450M in funding from leading investors including Altimeter Capital, Redpoint Ventures, and T. Rowe Price, with an additional $500M in signed contracts across commercial and US government customers. The company is mass-producing high-power satellite platforms for missions from LEO to deep space, capitalizing on the shift from mass-constrained to mass-abundant launch environments.
As a Senior ASIC Emulation Engineer, you will lead the bring-up, deployment, and optimization of pre-silicon emulation platforms, working closely with architecture, RTL design, DFT, DV, firmware, physical design, and silicon validation teams. This is a hands-on role with high ownership and deep technical engagement in shaping first-generation silicon and system methodology.
Key responsibilities include building and maintaining full-chip, multi-chip, and system-level emulation models on platforms such as Palladium, ZeBu, or Veloce; defining and evolving emulation strategy and methodology across the ASIC organization; working with RTL engineers to compile, map, and optimize designs for emulation performance and capacity; developing transactors, BFMs, speed adapters, and virtualization interfaces; supporting system-level testing through full hardware/software integration; accelerating verification throughput by enabling DV teams to run targeted tests in emulation; enabling firmware and software teams with robust emulation platforms; running emulation workloads, triaging failures, and performing root-cause analysis; maintaining automation for compile flows and regression management; participating in architecture reviews and influencing design-for-emulation best practices; and supporting silicon bring-up and post-silicon validation through test reuse and pre/post-silicon correlation.
Required qualifications include a B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field; 5+ years of experience in ASIC/SoC development focused on emulation; solid understanding of SystemVerilog, digital logic, RTL flows, DV methodologies, and ASIC development lifecycles; hands-on expertise with major emulation platforms including model build, debug, and performance optimization; proficiency with scripting languages such as Python, Perl, and TCL; and experience with hardware/software interfaces, embedded processors, and firmware.
