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Salary: USD 150,000 - 250,000 / annual
Velaura is building next-generation compute technology for Physical AI—enabling robots, autonomous systems, drones, and intelligent machines to operate efficiently in the physical world. This role focuses on designing and optimizing the memory subsystem of the Velaura SoC, a critical component since Physical AI workloads are memory-bound, with bandwidth, latency, and power in the memory path directly gating chip performance.
You will own significant portions of the memory subsystem design, working closely with architects, performance modelers, software engineers, verification engineers, physical design teams, and memory IP/PHY partners to transform architectural concepts into production silicon.
Key responsibilities include:
- Design, implement, and optimize RTL for memory controllers, fabric interfaces, and PHY integration logic
- Own memory controller and PHY integration, including DFI interfaces, initialization, training flows, calibration, and silicon bring-up
- Drive high-speed, low-power design of the memory path: timing closure at high data rates, power-state management (self-refresh, power-down), clock/power gating, and DVFS interactions
- Work with software teams to define hardware interfaces, memory maps, and performance-critical interactions (scheduling, prefetching, QoS)
- Analyze bandwidth, latency, and utilization bottlenecks; propose architectural and implementation improvements
- Optimize for performance, power, area, scalability, and reliability (RAS features like ECC and error reporting)
- Partner with verification, physical design, and vendor teams throughout development and silicon bring-up
- Leverage modern engineering tools, including AI-assisted development workflows
- Participate in design reviews and contribute to technical excellence
This is a senior individual-contributor role with broad technical scope and influence across the memory subsystem architecture and implementation.
REQUIREMENTS:
- Hands-on experience designing RTL for complex digital systems, with ownership of memory subsystem blocks
- Demonstrated experience integrating a memory controller with a memory PHY, including DFI interfaces, initialization/training sequences, and bring-up
- Strong understanding of high-speed, low-power memory technologies (LPDDR4, LPDDR4X, LPDDR5, LPDDR5X, DDR, HBM), including protocol, timing, and power-state behavior
- Strong understanding of computer architecture, microarchitecture, and digital design fundamentals
- Expert-level Verilog and SystemVerilog skills; experience with modern RTL design methodologies (lint, clock-domain crossing analysis, synthesis-aware coding, low-power intent)
- Familiarity with performance, power, and area tradeoffs in the memory path
- Strong debugging and problem-solving skills
- Ability to work effectively in collaborative, multidisciplinary engineering environments
PREFERRED QUALIFICATIONS:
- Familiarity with standard interconnect protocols (AXI, CHI, ACE) and QoS mechanisms
- Experience with memory controller and PHY bring-up on silicon, including training/calibration debug and margining
- Knowledge of reliability, availability, and serviceability (RAS) in the memory path (inline/side-band ECC, scrubbing, poisoning, error reporting)
- Experience with low-power design techniques and power management architectures
- Experience developing a memory controller from the ground up (command scheduling, arbitration, bank/rank management, refresh, reordering)
- Knowledge of functional safety standards (ISO 26262, ASIL) as applied to memory-path design
- Experience with AI/ML or edge AI hardware, especially tensor workload memory access patterns
- Familiarity with robotics, drones, autonomous vehicles, or industrial automation
- Exposure to performance modeling, emulation, FPGA prototyping, or silicon bring-up
- Experience using modern AI tools and workflows to accelerate engineering productivity
