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Salary: USD 180,000 - 220,000 / annual
Atom Computing is building quantum computers using arrays of optically trapped neutral atoms. We are seeking a Principal ASIC Verification Engineer to lead functional verification of ASICs used in our quantum computing systems.
In this role, you will own block-to-chip verification plans, schedules, and signoff criteria, leading test development and execution across engineers and contractors. You will provide technical direction and mentorship to engineers, review test plans and code, and participate in candidate interviews. You will define contractor scope, milestones, and acceptance criteria, reviewing deliverables and overseeing integration and handoff.
Key responsibilities include developing Python testbenches, reusable drivers, monitors, reference models, and scoreboards integrated with RTL simulators. You will implement tests, automate regressions, debug failures, and close coverage gaps. You will lead post-layout gate-level verification, including netlist preparation, SDF annotation, and timing-accurate simulation. You will verify test modes and patterns with DFT, design, and physical design teams, resolving timing and signoff issues. You will resolve requirements and interface issues with architecture, RTL, firmware, and hardware teams, and support silicon bring-up and validation. You will communicate verification status, unresolved defects, and tapeout risks to stakeholders.
REQUIREMENTS:
- Bachelor's degree in electrical engineering, computer engineering, computer science, or related field (or equivalent experience)
- 10+ years of ASIC/SoC verification experience (15+ preferred)
- Experience verifying multiple ASICs through tapeout and subsequent silicon evaluation
- Block-to-chip verification experience with registers, data paths, and firmware interfaces
- Strong Python skills for reusable, object-oriented testbenches with constrained-random stimulus, simulation control, checkers, and coverage
- Ability to build behavioral models of mixed-signal blocks, including digital interfaces and timing
- Experience turning design requirements into verification plans, writing SystemVerilog assertions, and closing functional and code coverage
- Hands-on post-P&R experience preparing netlists and cell/memory models, annotating SDF, and debugging timing simulations
- DFT verification experience with test modes and flows (scan shift/capture, ATPG patterns, MBIST, JTAG)
- Strong RTL and waveform debugging skills (resets, clock domains, X propagation, timing checks)
- Proficiency with SystemVerilog/UVM, HDL debug tools, Linux, and version control
- Experience with regression automation, failure reproduction, and triage
PREFERRED:
- Technical leadership through ASIC tapeout, including mentoring, leading reviews, coordinating verification work, and communicating risks
- Experience directing verification contractors and reviewing delivery against quality and schedule commitments
- Silicon bring-up or validation experience, including lab debug and correlating hardware failures with simulation
- Experience with formal verification, equivalence checking, CDC/RDC, lint, emulation, or FPGA prototyping
- Familiarity with real-time control, signal processing, or quantum hardware
