SlipstreamJobs tracks this role from the company's public career site. Apply directly on the employer's site.
Etched is building custom hardware for frontier AI inference, co-designing chips, racks, software, and manufacturing to optimize throughput and latency. The Power Integrity Engineer will own the power delivery network (PDN) methodology for high-power PCB and system designs, from early architecture through final release, ensuring robust power delivery to high-performance ASICs and supporting components across all operating conditions.
Key responsibilities include performing pre- and post-layout PDN analysis for high-current ASIC power rails, including target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis. You will execute DC IR-drop and current density simulations, define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers. The role involves conducting AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.
You will develop and validate VRM models, analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications. Responsibilities include performing power-plane thermal co-simulation and working with mechanical teams on thermal-electrical tradeoffs for high-current delivery. You will drive design rule checks for PI compliance and work with layout teams in Cadence Allegro, Sigrity PowerDC/PowerSI, or Ansys SIwave.
Collaboration is essential—you will work with power design, PCB layout, and ASIC/package teams to define power delivery architecture and review guidelines early in the product lifecycle. You will support bring-up, debug rail-level issues (droop, ripple, transient excursions), and document root-cause findings with clear corrective actions. The role includes developing and maintaining simulation-to-hardware correlation databases to continuously improve PDN modeling accuracy.
Required qualifications: B.S. or M.S. in Electrical Engineering or closely related discipline; 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms); proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent); strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation; experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity; working knowledge of VRM fundamentals and multi-layer PCB stack-up design.
Nice-to-have qualifications include prior work in data center, AI/ML accelerator, networking, or HPC hardware environments; experience with vertical power delivery or 48V-to-point-of-load architectures; package-level PDN co-analysis; and scripting automated PI simulation flows using Python or MATLAB.
