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As a Staff Physical Verification Engineer at Velaura AI (Auradine), you will own block-level and full-chip physical verification and signoff for next-generation AI and high-performance computing silicon. This is a highly technical, hands-on role requiring deep expertise in DRC, LVS, ERC, PERC, antenna, ESD/EOS, and reliability verification across complex SoC designs targeting advanced process technologies (FinFET, GAA).
Key responsibilities include:
- Own end-to-end physical verification signoff from block-level implementation through full-chip integration and tape-out
- Drive tape-out readiness through violation triage, root-cause analysis, waiver management, and convergence to zero violations
- Execute and debug PV using Siemens Calibre and Synopsys IC Validator, correlating results with Cadence Innovus and Synopsys Fusion Compiler
- Perform hands-on physical implementation and ECO changes: routing, via edits, metal-shape modifications, cell movement, power-grid updates
- Define and enhance PERC and reliability verification flows for ESD, EOS, latch-up, and current-density constraints
- Develop Tcl and Python/Perl/Unix automation for violation analysis, ECOs, PV execution, and signoff reporting
- Drive PV closure for advanced nodes including restrictive spacing, coloring, EUV, and multi-patterning requirements
- Influence floorplanning and power-grid planning from a PV perspective to minimize late-stage violations
- Support hierarchical and full-chip methodologies for digital-on-top, mixed-signal, and multi-voltage SoCs
- Partner with Physical Design, STA, Power Integrity, Analog, Reliability, and CAD teams to ensure PV changes preserve timing, congestion, routability, and design functionality
- Mentor engineers on PV methodology, advanced-node debugging, and tape-out best practices
- Collaborate with foundries and EDA vendors to qualify technology nodes and resolve complex PV issues
Required: Bachelor's or Master's in EE/VLSI; 8+ years in physical verification for complex ASIC/SoC designs with multiple production tape-outs; proven block/full-chip PV signoff ownership; strong hands-on DRC/LVS experience with exposure to PERC and reliability verification; experience with advanced FinFET/GAA technologies and at least one production tape-out at advanced nodes; expertise with Calibre and/or Synopsys ICV; ability to perform manual and scripted ECO changes in Innovus/Fusion Compiler; strong Tcl and Python/Perl/Unix scripting skills; deep understanding of how PV changes impact timing, congestion, routability, signal integrity, power integrity, and reliability; excellent debugging and root-cause analysis skills; strong cross-functional communication.
Preferred: Hands-on PERC-based reliability verification experience; Cadence Virtuoso integration with Calibre/ICV for analog/mixed-signal; hierarchical and full-chip PV signoff for digital-on-top and mixed-signal designs.
