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Salary: USD 200,000 - 300,000 / annual
Positron AI is building next-generation AI inference accelerators designed for low-latency, high-throughput large language model inference. The company recently raised $875 million at a $5 billion valuation (September 2026) and is bringing its custom Asimov ASIC and Titan system to market.
You will own synthesis, timing convergence, and implementation readiness for key partitions across the AI accelerator roadmap. This is a hands-on engineering role responsible for turning high-quality RTL into implementation-ready netlists, developing and maintaining timing constraints, and driving physical-aware optimization in close collaboration with RTL designers and backend implementation partners. You will serve as a key technical link between architecture, RTL, verification, and physical implementation.
Key responsibilities include:
**Synthesis Execution & Methodology**: Own synthesis for assigned partitions and subsystems, delivering clean, high-QoR netlists on schedule. Contribute to the development and improvement of synthesis flows, including constraint development, timing budgeting, QoR optimization, incremental synthesis, and hierarchical implementation. Help define and apply signoff criteria for synthesis deliverables.
**Hands-On Synthesis & Constraint Development**: Run hands-on synthesis using industry-leading EDA tools, including Cadence Genus and Synopsys Design Compiler. Develop and maintain SDC constraints, clock definitions, false paths, multicycle paths, generated clocks, and MMMC environments. Track and continuously improve synthesis QoR for your blocks.
**Timing Closure**: Drive logical timing closure for assigned partitions, optimizing across frequency, area, power, congestion, and wireability. Perform root-cause analysis of timing bottlenecks and contribute to chip-level timing budgets. Work with architecture and RTL teams to identify and resolve timing risks before physical implementation.
**Physical-Aware Optimization**: Partner with backend implementation engineers on physical-aware synthesis, retiming, register balancing, pipeline optimization, and logic restructuring. Give RTL teams actionable feedback so designs are implementation-friendly from the outset.
**Cross-Functional Execution**: Collaborate with architecture, RTL, verification, physical design, DFT, IP providers, and backend design services to drive rapid issue resolution.
**Vendor Collaboration**: Work with external implementation partners to review QoR, timing, and area reports, and support constraint methodology and acceptance criteria.
**AI-Enabled Engineering**: Apply AI tools to improve timing analysis, QoR regression, constraint generation, timing debug, report analysis, documentation, and engineering automation.
**Requirements:**
- 8+ years of ASIC implementation experience, including at least two successful tapeouts
- Strong hands-on proficiency in synthesis and flow development
- Proven experience closing timing on complex, multi-million-gate designs
- Deep working knowledge of Cadence Genus and/or Synopsys Design Compiler
- Strong SDC expertise, including constraint development and MMMC environments
- Solid grasp of RTL design principles and implementation-friendly coding practices
- Hands-on experience with advanced process nodes (7nm and below preferred)
- Strong Tcl and Python scripting ability for automation and flow development
- Excellent debugging and root-cause analysis skills
