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Etched is building custom AI inference hardware—chips, racks, software, and manufacturing—optimized for throughput and latency across prefill and decode workloads. As a Physical Design Engineer, you will own block-level and subsystem implementation from RTL synthesis through GDSII sign-off, driving PPA optimization and collaborating closely with RTL designers to accelerate iteration cycles.
Key responsibilities include: end-to-end physical design ownership (floorplanning, synthesis, placement, clock tree synthesis, routing); timing closure across all corners and modes with constraint development and STA debug; signoff across EM, IR drop, RC extraction, and physical verification (DRC, LVS, antenna); generation of abstracts, views, and timing budgets for hierarchical integration; collaboration with RTL teams to provide actionable physical design feedback; continuous PPA improvement and flow optimization; and supervision of outsourced physical design work to third-party vendors.
You bring 5–10+ years of physical design experience with deep expertise in RTL-to-GDSII flows on advanced nodes (5nm and below). You are proficient with Cadence (Innovus, Genus) or Synopsys (Fusion Compiler) tools, sign-off tools (PrimeTime, Tempus, Voltus), and UPF-based low-power design. You have strong scripting skills (Tcl, Python, Perl) for flow automation and debug, and you think creatively from first principles. Familiarity with ML/LLM architectures, Python programming, and startup environments is a plus.
The role is based in Austin with regular collaboration at the San Jose headquarters—approximately two weeks per month during the first quarter, then one week per month ongoing. Etched offers medical/dental/vision coverage, $500/month benefits waiver credit, $2k/month housing subsidy for those near the office, relocation support, wellness benefits, daily meals, and unlimited compute budget subject to ROI justification.
