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OpenAI's Hardware organization is developing AI-native silicon and system-level solutions for advanced AI workloads. This role is a senior individual contributor position within the physical design team, responsible for delivering power, performance, and area (PPA) optimized datapath and interconnect solutions for next-generation AI accelerators.
You will develop, build, and own tools, flows, and methodologies for physical implementation, directly impacting silicon performance, cost efficiency, and team execution velocity. Key responsibilities include:
- Develop and own tools, flows, and methodologies for physical implementation
- Own physical implementation of floorplan blocks from floorplanning through final signoff
- Collaborate with RTL designers to drive optimal block implementation solutions
- Analyze and optimize designs for timing, power, and area trade-offs in partnership with EDA vendors and ASIC partners
- Work closely with RTL designers to define and execute physical design strategies
This role sits at the intersection of chip design, system architecture, and tooling development. You will have direct impact on OpenAI's supercomputing platform and the efficiency of frontier AI models.
REQUIREMENTS:
- BS with 4+ years, MS with 2+ years, or PhD with 0-1 year(s) of relevant industry experience in physical design and methodology development
- Demonstrated success in taping out complex silicon designs
- Hands-on experience with block physical implementation and PPA convergence
- Strong coding experience with Python, Bazel, and TCL
- Strong experience building physical design tools, flows, and methodologies
- Strong understanding of microarchitecture, RTL design, physical design, circuit design, physical verification, and timing closure
- Deep familiarity with industry-standard tools and flows for physical synthesis, place-and-route (PNR), logic equivalence checking (LEC), and power estimation
BONUS QUALIFICATIONS:
- Experience with AI or HPC-focused chips
- Experience optimizing PPA for high-performance compute cores
- Hands-on experience with top-level design methodologies
Note: Candidates may need to meet certain legal status requirements to comply with U.S. export control laws and regulations.
