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Salary: USD 180,000 - 260,000 / annual
Delos Data is seeking a Principal Physical Design Engineer to join as an early member of the physical design team. This is a deeply hands-on, technical leadership role for an experienced engineer who can independently drive complex chip design from floorplan through signoff.
You will own physical implementation of critical blocks and subsystems, developing floorplans that balance hierarchy, macros, interfaces, congestion, timing, power, and routability. Key responsibilities include driving placement, optimization, clock-tree synthesis, routing, extraction, timing closure, and ECO implementation. You will own difficult setup, hold, signal-integrity, and congestion problems, and lead timing closure across block boundaries to support top-level convergence.
You will perform static timing analysis across multiple modes and corners, support signal-integrity analysis accounting for crosstalk and variation, and drive physical signoff including DRC, LVS, antenna checks, density, and connectivity verification. Power integrity analysis—including static and dynamic IR drop and electromigration—is also part of the scope. You will develop implementation strategies for high-performance and physically challenging design portions, partner with RTL and architecture teams to identify problems early, and work cross-functionally with DFT, verification, package, SI/PI, and other teams.
Beyond hands-on implementation, you will develop and improve physical design flows, scripts, automation, metrics, and methodologies. You will evaluate results to identify PPA, runtime, convergence, and design-quality improvements, provide technical guidance and mentorship to other physical design engineers, and serve as a technical escalation point for complex issues. You will participate in design reviews, methodology reviews, and tapeout readiness assessments.
REQUIREMENTS:
- 10+ years of ASIC or SoC physical design experience with multiple successful tapeouts
- Expert-level understanding of floorplanning, placement, CTS, routing, optimization, timing closure, ECOs, and physical verification
- Strong expertise in static timing analysis and multi-mode, multi-corner timing closure
- Strong understanding of power delivery, IR drop, electromigration, and signal integrity
- Demonstrated ability to independently own complex blocks or major portions of a chip through signoff
- Strong understanding of clock design, timing constraints, variation, extraction, and advanced-node physical effects
- Experience with industry-standard Cadence and/or Synopsys physical implementation and signoff tools
- Strong scripting and automation skills using Tcl, Python, Perl, or similar languages
- Ability to debug complex design problems across RTL, timing, physical implementation, and signoff domains
- Strong communication skills and ability to provide technical leadership without requiring formal management authority
DESIRED:
- Experience with advanced process nodes
- Experience with large, high-frequency, or highly interconnected semiconductor designs
- Experience with hierarchical design and top-level physical integration
- Experience developing physical design methodologies and automation
- Experience working closely with package, SI/PI, and power-delivery teams
- Experience with multi-die, chiplet, or advanced packaging architectures
- Familiarity with EDA tool evaluation, benchmarking, and optimization
- Experience in an early-stage semiconductor environment
