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Salary: USD 129,000 - 0 / annual
Anduril Industries is seeking a PCB Layout Engineer to join the Intelligence Systems division in Reston, Virginia. This role focuses on full-cycle PCB design for specialized defense and intelligence community applications, including requirements gathering, schematic design, component selection, layout supervision/completion, bring-up, testing, debug, and system integration.
Key responsibilities include:
- Collaborating with engineers to produce printed circuit board designs for Anduril's advanced defense products
- Applying modern design standards to create high-reliability, highly manufacturable assemblies
- Implementing complex combinations of high-speed digital, precision analog, RF, and high-power designs
- Establishing and refining internal guidelines for design for manufacturing (DFM), design for assembly (DFA), and quality standards
- Improving team processes for PCB design, component creation, and library/database management
- Coordinating external PCB design resources during design surges
- Managing multiple concurrent projects in a fast-paced environment
Required qualifications include an Associate's degree in electrical engineering or equivalent plus 5+ years of professional PCB layout design experience. Candidates must demonstrate expertise in IPC standards (CID/CID+ certification), PCB fabrication processes, Altium Designer CAD tools, and component library development. Experience with high-density boards, high layer count designs (16+), power electronics, flex circuits, RF circuits, HDI, signal/power integrity, and high-speed digital interfaces (USB, PCIe, Ethernet) is essential. Candidates must be eligible to obtain and maintain an active U.S. Secret security clearance.
Preferred qualifications include experience with dense high-pin count packages (FPGA fanout), high-speed digital interfaces and SERDES, SoC FPGAs, Siemens Xpedition or Cadence Allegro ECAD tools, sequential lam structures, and air-gapped network environments.